ADC input settling calculator

Estimate the remaining voltage error when an ADC sampling capacitor enters hold.

Schematic

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Results

Residual settling error22.24 mV

The acquisition window is too short for 12-bit settling to within half an LSB.

Acquisition followed by hold

Sampling capacitor

Acquired voltage	3.28 V
Error in 12-bit LSBs	27.6
Time for ½ LSB at 12 bits	1.8 µs

Advanced results

Full-scale error	0.67 %
RC time constant	200 ns

How adc input settling works

R1 includes source and input-switch resistance. C1 models the sampling capacitor. The sampling switch closes for V2’s pulse width, then holds the acquired voltage. Compare the selected acquisition time with the half-LSB requirement for a 12-bit full-scale step.

V_{error}=V_1e^{-t_{acq}/(R_1C_1)}

First-order RC model, initially discharged capacitor, ideal hold and negligible switch resistance. Fixed 12-bit comparison, not a complete ADC model; leakage, kickback, driver dynamics and conversion noise are excluded.

Change the form inputs or click a component value on the schematic. Choose Try in CircuitSim to simulate the configured circuit.

Do the math

Selected input values
R1	10 kΩ
C1	20 pF
V2	1 µs
V1	3.3 V

RC time constant: $\tau=R_1C_1$
$10\,\mathrm{k\Omega}\times20\,\mathrm{pF}$
≈ 200 ns
Held error: $V_{error}=V_1e^{-t_{acq}/(R_1C_1)}$
$3.3\,\mathrm{V}e^{-5}$
≈ 22.24 mV
12-bit half-LSB acquisition: $t_{acq}\ge (12+1)\ln(2)\tau$
$13\ln(2)\times200\,\mathrm{ns}$
≈ 1.8 µs

ADC input settling calculator

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Schematic

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How adc input settling works

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