THE CIRCUIT

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
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R_R1 N3 0 1K Resistor_1d9c8cf9a__R_R1
xSW1 N1 N3 N2 CS_IDEAL_SCR PARAMS: Vth=2 Ih=10m Vfscr=0 Ron=10m Roff=10meg
V_V1 N1 0 dc 5 ac 0 0 distof1 0 0 distof2 0 0
V_V2 N2 N3 ac 1 0 distof1 0 0 distof2 0 0 pulse(0 5 0 1n 1n 10u 10u )

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* Models and supporting definitions follow
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.model Resistor_1d9c8cf9a__R_R1 r(tc1=0 tc2=0 tnom=27)
.subckt CS_IDEAL_SCR Anode Cathode Gate params: Vth=2.5 Ih=10m Vfscr=0 Ron=10m Roff=10Meg
    * Supported analog SCR approximation with gate-triggered holding-current memory.
    VSENSE Anode AS 0
    VON ON Cathode 5
    SGATE ON SET Gate Cathode CS_SCR_GATE
    CSTATE SET Cathode 1u IC=0
    RRESET SET Cathode 1k
    BHOLD Cathode SET I={I(VSENSE)>=Ih ? V(SET,Cathode)/1k : 0}
    SMAIN AS DF SET Cathode CS_SCR_SWITCH
    DMAIN DF VF CS_SCR_DIODE
    BVF VF Cathode V={Vfscr}
    ROFF Anode Cathode {Roff}
    RGK Gate Cathode 100Meg
    .model CS_SCR_GATE SW(Ron=10 Roff=1G Vt={Vth} Vh=0.1)
    .model CS_SCR_SWITCH SW(Ron={Ron} Roff={Roff} Vt=2.5 Vh=0.25)
    .model CS_SCR_DIODE D(Is=1e-14 N=1m Rs=1u)
.ends CS_IDEAL_SCR

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* Simulation settings
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.tran 20u 100m 0 20u
.end