New Circuit1

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
xD1 N3 N2 ESD108B1CSP0201IFX_9429a604
xQ1 N2 N3 0 Param2N7000ON_3a210cad
X_U1 N2 NC_1 NC_2 Param3TVIRTUAL_5a7fc2f7 IOS=0 AVOL=200K BW=100meg VOS=0 IBS=0 RI=10meg VOMP=12 VOMN=-12 RO=10
V_V1 N3 0 dc 5 ac 0 0 distof1 0 0 distof2 0 0

**************************************************
* Models and supporting definitions follow
**************************************************
.subckt ESD108B1CSP0201IFX_9429a604 T0 T1
    XADAPTER T0 T1 ESD108B1CSP0201IFX_9429a604_SOURCE
.ENDS ESD108B1CSP0201IFX_9429a604
.MODEL ESD108B1CSP0201IFX_9429a604_DF D
+ IS = 6E-016
+ N = 1
+ RS = 0.7
+ BV = 100
+ IBV = 0.001
+ CJO = 5E-014
+ VJ = 0.1854
+ M = 0.5
+ FC = 0.5
+ TT = 5E-006
+ EG = 1.1
+ XTI = 3
.MODEL ESD108B1CSP0201IFX_9429a604_DS D
+ IS = 1E-013
+ N = 1
+ RS = 1
+ BV = 100
+ IBV = 0.001
+ CJO = 4.8E-013
+ VJ = 0.8
+ M = 0.5
+ FC = 0.5
+ TT = 3E-006
+ EG = 1.11
+ XTI = 3
.MODEL ESD108B1CSP0201IFX_9429a604_DZ D
+ IS = 1E-016
+ N = 1
+ RS = 2
+ BV = 100
+ IBV = 1E-006
+ CJO = 4.8E-012
+ VJ = 0.7
+ M = 0.12
+ FC = 0.5
+ TT = 0
+ EG = 1.11
+ XTI = 3
.MODEL ESD108B1CSP0201IFX_9429a604_DT D
+ IS = 5E-013
+ N = 40
+ RS = 0
+ BV = 100
+ IBV = 0.001
+ CJO = 0
+ VJ = 0.8
+ M = 0.5
+ FC = 0.5
+ TT = 0
+ EG = 18
+ XTI = 10
.MODEL ESD108B1CSP0201IFX_9429a604_DHC D
+ IS = 1E-018
+ N = 1
+ RS = 0.47
+ BV = 6.523
+ IBV = 0.002
+ CJO = 0
+ TT = 0
*******************************************************************
*
* INFINEON SPICE MODEL LIBRARY for TVS DIODES
*
* Version 2.1
* Date 2015/12/14
*
* Copyright (C) 2015 by Infineon Technologies AG, Neubiberg, Germany
* all rights reserved
*
*
* This library contains the following TVS DIODE models:
*
* DSL70 ESD113_B1_02ELS ESD207_B1_02ELS
* ESD101_B1_02EL ESD119_B1_W01005 ESD208_B1_02EL
* ESD101_B1_02ELS ESD128_B1_W0201 ESD208_B1_02ELS
* ESD102_U1_02ELS ESD129_B1_W01005 ESD217_B1_02EL
* ESD102_U4_05L ESD200_B1_CSP0201 ESD218_B1_02EL
* ESD103_B1_02EL ESD202_B1_CSP01005 ESD218_B1_02ELS
* ESD103_B1_02ELS ESD203_B1_02EL ESD221_U1_02EL
* ESD105_B1_02EL ESD203_B1_02ELS ESD231_B1_W0201
* ESD105_B1_02ELS ESD204_B1_02EL ESD24VS2U
* ESD108_B1_CSP0201 ESD204_B1_02ELS ESD300_B1_02LRH
* ESD110_B1_02EL ESD205_B1_02EL ESD307_U1_02N
* ESD110_B1_02ELS ESD206_B1_02EL ESD311_U1_02N
* ESD112_B1_02EL ESD206_B1_02ELS ESD5V3U4RRS
* ESD112_B1_02ELS ESD206_B1_02V ESD5V5U5ULC
* ESD113_B1_02EL ESD207_B1_02EL TVS3V3L4U
*
*******************************************************************
*************************************************************************
*
* SPICE model for Infineon TVS diode ESD108_B1_CSP0201 (Bi-directional TVS diode)
* Version 2.0 / 2013-11-21
*
* Usage: X<instancename> <pin1_node> <pin2_node> ESD108_B1_CSP0201
*
* This model is using Berkeley Spice3 syntax
* Model parameters are extracted using Berkeley Spice3
*
* The model is extracted using:
* - leakage current data (room temperature)
* - capacitance(voltage) data (1 MHz room temperature)
* - S-Parameter data (0V bias, 10 MHz - 40 GHz10room temperature)
* - 100ns TLP data (room temperature).
* The model includes the ESD clamping behavior.
* The model does not include transient voltage overshoot effects,
* and does not include snap-back behavior.
*
* Copyright (C) 2013 by Infineon Technologies AG, Neubiberg, Germany
* all rights reserved
*************************************************************************
.subckt ESD108B1CSP0201IFX_9429a604_SOURCE 1 2
    X1 1 10 ESD108B1CSP0201IFX_9429a604_ESD108_B1_CSP0201_uni
    X2 2 10 ESD108B1CSP0201IFX_9429a604_ESD108_B1_CSP0201_uni
    *
.ENDS ESD108B1CSP0201IFX_9429a604_SOURCE
.SUBCKT ESD108B1CSP0201IFX_9429a604_ESD108_B1_CSP0201_uni 1 2
    * single diode subcircuit SD
    * note: n - substrate
    *
    * o 1
    * ||
    * o---------o-------------------o
    * || || ||
    * || --- ||
    * || / \DS ||
    * || --- ||
    * || || ||
    * || 24 o--------o ||
    * || || || ||
    * || - || ||
    * || || || || ||
    * || || || --- ||
    * || || || --- ||
    * || || || || ||
    * || - || ||
    * || || || ||
    * || 23 o--------o ||
    * || || || ||
    * --- ---z --- ---
    * \ / DF \ / DZ / \DT \ / DHC
    * --- --- --- ---
    * || || || ||
    * || || || ||
    * o---------o--------o----------o
    * ||
    * ||
    * o 2
    *
    *DF Diode modeling the forward mode
    *DS Anti series diode to DZ reducing the capacitance
    *DZ Zener diode conducting the ESD pulse
    *DT Tunnel current of the Zener diode
    *DHC Diode to model the tlp HC behavior
    * diode call syntax: instance, anode(+), cathode(-), modelname
    D1 24 11
    + ESD108B1CSP0201IFX_9429a604_DS
    D2 23 2
    + ESD108B1CSP0201IFX_9429a604_DZ
    D3 2 23
    + ESD108B1CSP0201IFX_9429a604_DT
    D4 11 2
    + ESD108B1CSP0201IFX_9429a604_DF
    D5 11 2
    + ESD108B1CSP0201IFX_9429a604_DHC
    cp 1 2 1E-014
    ls 1 11 1E-012
    c1 24 234 1.2E-012
    r1 24 234 110
    c2 234 23 1.675E-012
    r2 234 23 24
    *
.ENDS ESD108B1CSP0201IFX_9429a604
.subckt Param2N7000ON_3a210cad D G S
    XADAPTER D G S Param2N7000ON_3a210cad_SOURCE
.ENDS Param2N7000ON_3a210cad
.MODEL Param2N7000ON_3a210cad_MM NMOS LEVEL=1 IS=1e-32
+VTO=2.236 LAMBDA=0 KP=0.0932174
+CGSO=1.79115e-07 CGDO=1.0724e-11
.MODEL Param2N7000ON_3a210cad_MD D IS=2.71011e-10 RS=0.0140826 N=1.5 BV=60
+IBV=1e-05 EG=1.16084 XTI=3.00131 TT=0
+CJO=3.41211e-11 VJ=4.67429 M=0.899864 FC=0.1
.MODEL Param2N7000ON_3a210cad_MD1 D IS=1e-32 N=50
+CJO=7.93181e-11 VJ=0.643298 M=0.9 FC=1e-08
.MODEL Param2N7000ON_3a210cad_MD2 D IS=1e-10 N=0.400165 RS=3.00002e-06
.MODEL Param2N7000ON_3a210cad_MD3 D IS=1e-10 N=0.400165
.subckt Param2N7000ON_3a210cad_SOURCE 1 2 3
    **************************************
    * Model Generated by MODPEX *
    *Copyright(c) Symmetry Design Systems*
    * All Rights Reserved *
    * UNPUBLISHED LICENSED SOFTWARE *
    * Contains Proprietary Information *
    * Which is The Property of *
    * SYMMETRY OR ITS LICENSORS *
    *Commercial Use or Resale Restricted *
    * by Symmetry License Agreement *
    **************************************
    * Model generated on Mar 31, 04
    * MODEL FORMAT: PSpice
    * Symmetry POWER MOS Model (Version 1.0)
    * External Node Designations
    * Node 1 -> Drain
    * Node 2 -> Gate
    * Node 3 -> Source
    M1 9 7 8 8 Param2N7000ON_3a210cad_MM L=100u W=100u
    * Default values used in MM:
    * The voltage-dependent capacitances are
    * not included. Other default values are:
    * RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0
    RS 8 3 1.10523
    D1 3 1 Param2N7000ON_3a210cad_MD
    RDS 3 1 2.4e+11
    RD 9 1 0.0001
    RG 2 7 2.18034
    D2 4 5 Param2N7000ON_3a210cad_MD1
    * Default values used in MD1:
    * RS=0 EG=1.11 XTI=3.0 TT=0
    * BV=infinite IBV=1m
    D3 0 5 Param2N7000ON_3a210cad_MD2
    * Default values used in MD2:
    * EG=1.11 XTI=3.0 TT=0 CJO=0
    * BV=infinite IBV=1m
    RL 5 10 1
    FI2 7 9 VFI2 -1
    VFI2 4 0 0
    EV16 10 0 9 7 1
    CAP 11 10 1.58786e-10
    FI1 7 9 VFI1 -1
    VFI1 11 6 0
    RCAP 6 10 1
    D4 0 6 Param2N7000ON_3a210cad_MD3
    * Default values used in MD3:
    * EG=1.11 XTI=3.0 TT=0 CJO=0
    * RS=0 BV=infinite IBV=1m
.ENDS Param2N7000ON_3a210cad_SOURCE
.model Param3TVIRTUAL_5a7fc2f7_D1 d(n=0.1)
.subckt Param3TVIRTUAL_5a7fc2f7 in_pos in_neg out params: VOS=0 IBS=0 IOS=0 AVOL=200K BW=100M RI=10M RO=10 VOMP=12 VOMN=-12

    * Input Stage: Rin, Ibias, Voffset
    VOS in_pos 4 {VOS}
    Ibias1 4 0 {IBS}
    Ibias2 in_neg 0 {IBS}
    IOS 4 in_neg {IOS/2}
    Rin 4 in_neg {RI}

    *Middle stage: Gain, frequency, voltage limiting
    Bgain 0 6 I={v(4,in_neg)*AVOL/1meg}
    R1 6 0 1meg
    CP1 6 0 {AVOL/(2*3.141592653589793*1meg*BW)}


    Vpos 9 0 {VOMP}
    Dlimit_pos 6 9 Param3TVIRTUAL_5a7fc2f7_D1

    Vneg 10 0 {VOMN}
    Dlimit_neg 10 6 Param3TVIRTUAL_5a7fc2f7_D1


    *Output stage: Buffer, output resistance
    E2 7 0 6 0 1
    Rout 7 out {RO}
.ends

**************************************************
* Simulation settings
**************************************************
.tran 0.000001 100m 0 200p
.end