High-Pass Filter (RC)
CircuitSim
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Created Oct 3, 2026
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Updated Oct 3, 2026
Details
Components
3
Schematic
Yes
Simulation
Transient analysis
Copies
Not copied yet
About this circuit
Compare a sinusoidal input with the attenuated, phase-leading output of an RC high-pass filter.
Circuit notes
High-Pass Filter (RC)
A series capacitor blocks DC and attenuates slowly changing signals. The resistor provides a return path and converts capacitor current into the output voltage. This arrangement is useful for AC coupling between stages.
Schematic and source
V1 on the left is a 1 V peak, 1 kHz sine wave, with zero DC offset. C1 (100 nF) is in series along the top. R1 (1 kΩ) returns the output to ground on the right. Vin is green, Vout is red and Iin is blue. Current is positive from the source through C1 toward R1.
Expected waveform
For , the unloaded transfer function and cutoff are:
At 1 kHz, the output is 0.53202 V peak and leads the input by 57.858°. Since R1 is 1 kΩ, Iin has the same phase as Vout and peaks at 0.53202 mA. The output leads in the periodic steady state because capacitor current depends on how quickly voltage changes.
Use the chart
The transient analysis runs from 0 to 40 ms, with a 2 µs maximum time step and zero initial capacitor voltage. The chart starts at 35–40 ms to show five settled cycles. Voltages share the upper axis; current has its own axis. Open Table to inspect time samples, or zoom out to see the brief startup response. The time constant is .
Try two changes
- Change V1 → Frequency from 1k to 2k and click Run simulation. Vout rises to about 0.7825 V peak and its phase lead decreases to about 38.51°. Restore 1k.
- Change C1 → Capacitance from 100n to 200n and run again. The cutoff halves to 795.77 Hz. At the original 1 kHz input, Vout is again about 0.7825 V peak. Restore 100n.
Keep R1 at 1k, source peak amplitude at 1 V and capacitor initial voltage at 0 V. The separate High-Pass Filter Response (RC) example shows the same network as a frequency sweep.
Model limits
The source and capacitor are ideal. The probes do not load the output; a real receiving stage in parallel with R1 changes the effective resistance and cutoff. No capacitor leakage, ESR or source output resistance is included.
Components used
Components used
3 components
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