RTL NAND

Series bipolar transistors pull the output low only when both logic inputs are high.

Circuit operation

Two transistors are stacked in the pull-down path. Each input has its own base resistor. RC pulls the output high unless both transistors conduct.

Expected behavior

$$Y=\overline{A B}$$ $$V_{OL}\approx V_{CE(sat),1}+V_{CE(sat),2}$$

All four input combinations occur during the saved run. Only two high inputs produce a low output. The series stack raises the low voltage and reduces the available noise margin compared with a single transistor.

Reading the results

The first voltage probe is green and the second is red. Additional voltage traces use distinct colors. Current probes, when present, start with blue and then purple. The chart opens with separate traces on a fixed time window; the table retains the same probe order. Zoom to extents includes the complete schematic.

The saved transient runs for 4.0 ms with a maximum step of 1.00 µs. Compare settled cycles after startup and use time-axis cursors to measure delays or periods.

Try a change

Set V1 period to 3 ms and pulse width to 1.45 ms; compare the truth table at the new input timing. Restore the saved values after comparing the result.

Model limits

These are generic transistor models, not a specific manufactured part. The bipolar models use nominal forward current gain 100 with illustrative junction capacitances and transit times. Device mismatch, temperature drift, layout parasitics, breakdown and detailed noise are not represented. The schematic and component properties expose the values used.