Exclusive OR

Combine AND, OR, and NOT gates to produce a high output exactly when two inputs differ.

Circuit operation

The two inverters provide complemented inputs. One AND gate detects A high and B low; the other detects A low and B high. The OR gate combines those mutually exclusive cases.

Expected behavior

$$Y=A\overline B+\overline A B$$ $$Y=A\oplus B$$

Y is high only for unequal inputs. The two pulse periods exercise 00, 01, 10, and 11. The gate-level construction makes the exclusive-OR function visible.

Reading the results

The first voltage probe is green and the second is red. Additional voltage traces use distinct colors. Current probes, when present, start with blue and then purple. The chart opens with separate traces on a fixed time window; the table retains the same probe order. Zoom to extents includes the complete schematic.

The saved transient runs for 8.0 ms with a maximum step of 2.00 µs. Compare settled cycles after startup and use time-axis cursors to measure delays or periods.

Try a change

Set V1 period to 3 ms and pulse width to 1.498 ms. Verify the same logic relationship with a different input sequence. Restore the saved values after comparing the result.

Model limits

Logic gates use ideal threshold models; storage elements include finite propagation delay. Unless a transistor or LED is explicitly drawn, internal supplies, input loading, output-current limits, and metastability are abstracted. Device mismatch, temperature drift, layout parasitics, breakdown and detailed noise are not represented. The schematic and component properties expose the values used.