1-of-4 Decoder

Convert a two-bit binary address into four mutually exclusive output lines.

Circuit operation

Two inverters provide the complemented address bits. Each AND gate recognizes one address combination, activating exactly one of Y0 through Y3.

Expected behavior

$$k=A_0+2A_1$$ $$Y_k=1,\qquad Y_{j\ne k}=0$$

A0 is the least-significant address bit. The sequence 00, 01, 10, 11 selects Y0, Y1, Y2, Y3. Evaluate one-hot behavior away from input transitions.

Reading the results

The first voltage probe is green and the second is red. Additional voltage traces use distinct colors. Current probes, when present, start with blue and then purple. The chart opens with separate traces on a fixed time window; the table retains the same probe order. Zoom to extents includes the complete schematic.

The saved transient runs for 8.0 ms with a maximum step of 2.00 µs. Compare settled cycles after startup and use time-axis cursors to measure delays or periods.

Try a change

Set V1 period to 3 ms and pulse width to 1.498 ms. Verify the same logic relationship with a different input sequence. Restore the saved values after comparing the result.

Model limits

Logic gates use ideal threshold models; storage elements include finite propagation delay. Unless a transistor or LED is explicitly drawn, internal supplies, input loading, output-current limits, and metastability are abstracted. Device mismatch, temperature drift, layout parasitics, breakdown and detailed noise are not represented. The schematic and component properties expose the values used.