2-to-1 Mux

Use a select signal to route either of two logic inputs to one output.

Circuit operation

The Select inverter enables the A path when Select is low. The B path is enabled when Select is high. Their AND outputs feed an OR gate.

Expected behavior

$$Y=\overline S A+SB$$ $$Y=\begin{cases}A,&S=0\\B,&S=1\end{cases}$$

The output copies A for Select = 0 and B for Select = 1. Changing the data inputs while their path is unselected does not change the settled output.

Reading the results

The first voltage probe is green and the second is red. Additional voltage traces use distinct colors. Current probes, when present, start with blue and then purple. The chart opens with separate traces on a fixed time window; the table retains the same probe order. Zoom to extents includes the complete schematic.

The saved transient runs for 8.0 ms with a maximum step of 2.00 µs. Compare settled cycles after startup and use time-axis cursors to measure delays or periods.

Try a change

Set V1 period to 3 ms and pulse width to 1.498 ms. Verify the same logic relationship with a different input sequence. Restore the saved values after comparing the result.

Model limits

Logic gates use ideal threshold models; storage elements include finite propagation delay. Unless a transistor or LED is explicitly drawn, internal supplies, input loading, output-current limits, and metastability are abstracted. Device mismatch, temperature drift, layout parasitics, breakdown and detailed noise are not represented. The schematic and component properties expose the values used.