Clocked SR Flip-Flop

Gate the set and reset commands so an SR latch responds only while its enable clock is high.

Circuit operation

Two AND gates qualify Set and Reset with Enable. Their outputs drive the cross-coupled NOR latch. The latch can respond throughout the high-enable interval.

Expected behavior

$$S_g=S\cdot E,\qquad R_g=R\cdot E$$ $$E=0\Rightarrow Q_{next}=Q$$

This is a level-sensitive gated latch, not an edge-triggered device. Commands during Enable = 0 are ignored unless they remain active when Enable rises. The saved commands overlap high-enable intervals without asserting Set and Reset together.

Reading the results

The first voltage probe is green and the second is red. Additional voltage traces use distinct colors. Current probes, when present, start with blue and then purple. The chart opens with separate traces on a fixed time window; the table retains the same probe order. Zoom to extents includes the complete schematic.

The saved transient runs for 8.0 ms with a maximum step of 2.00 µs. Compare settled cycles after startup and use time-axis cursors to measure delays or periods.

Try a change

Increase the active set interval by setting VS low-pulse width to 3.398 ms. Q still holds its state after the command ends. Restore the saved values after comparing the result.

Model limits

Logic gates use ideal threshold models; storage elements include finite propagation delay. Unless a transistor or LED is explicitly drawn, internal supplies, input loading, output-current limits, and metastability are abstracted. Device mismatch, temperature drift, layout parasitics, breakdown and detailed noise are not represented. The schematic and component properties expose the values used.