Dynamic RAM

Write and hold one bit as capacitor charge using a word-line-controlled MOS access transistor.

Circuit operation

WORD drives the gate of one n-channel access transistor. While WORD is high, DATA charges or discharges the 10 nF storage capacitor. When WORD goes low, the capacitor is isolated except for a 1 MΩ leakage resistor.

Expected behavior

$$Q=C_SV_S$$ $$V_S(t)=V_S(0)e^{-t/(R_{leak}C_S)}$$

A high data bit writes a storage voltage below 5 V because an n-channel pass transistor loses gate overdrive near the high rail. The stored voltage decays between accesses; a later low data bit discharges it. Real DRAM uses far smaller capacitors, differential sense amplifiers, precharge, and refresh; this one-cell example isolates charge storage and leakage.

Reading the results

The first voltage probe is green and the second is red. Additional voltage traces use distinct colors. Current probes, when present, start with blue and then purple. The chart opens with separate traces on a fixed time window; the table retains the same probe order. Zoom to extents includes the complete schematic.

The saved transient runs for 8.0 ms with a maximum step of 2.00 µs. Compare settled cycles after startup and use time-axis cursors to measure delays or periods.

Try a change

Set RLEAK to 100 kΩ; the stored high voltage decays much faster between refresh operations. Restore the saved values after comparing the result.

Model limits

Logic gates use ideal threshold models; storage elements include finite propagation delay. Unless a transistor or LED is explicitly drawn, internal supplies, input loading, output-current limits, and metastability are abstracted. Device mismatch, temperature drift, layout parasitics, breakdown and detailed noise are not represented. The schematic and component properties expose the values used.