555 Pulse Width Modulator

Vary the timer control-voltage threshold to modulate the duration of regularly triggered pulses.

Circuit operation

A 1 kHz trigger starts each monostable interval. VC drives CTRL with a 100 Hz sine wave around 2.5 V, changing the upper comparator threshold. RT and CT remain fixed.

Expected behavior

$$t_p=-R_TC_T\ln(1-\eta)$$ $$\begin{gathered}\eta=V_{CTRL}/V_{DD}\\D=t_p/T_{trigger}\end{gathered}$$

A higher control voltage makes CT charge farther before ending the pulse, increasing pulse width. With RT = 47 kΩ, CT = 10 nF, and CTRL varying from 1.5 to 3.5 V, the ideal pulse-width range is about 0.17–0.57 ms. The trigger repetition rate stays fixed.

Reading the results

The first voltage probe is green and the second is red. Additional voltage traces use distinct colors. Current probes, when present, start with blue and then purple. The chart opens with separate traces on a fixed time window; the table retains the same probe order. Zoom to extents includes the complete schematic.

The saved transient runs for 20.0 ms with a maximum step of 1.00 µs. Compare settled cycles after startup and use time-axis cursors to measure delays or periods.

Try a change

Set VC peak amplitude to 0.5 V; the pulse-width variation decreases. Restore the saved values after comparing the result.

Model limits

The packaged timer uses supply-relative comparators and a stateful latch with finite output (100 Ω) and discharge (20 Ω) resistance. It models timer behavior, not IC supply current or thermal limits. Timing estimates ignore those resistances, leakage, comparator delay, and component tolerances. The internals example is a functional explanation rather than a transistor-level IC replica. Device mismatch, temperature drift, layout parasitics, breakdown and detailed noise are not represented. The schematic and component properties expose the values used.

Reference: TI 555 timer datasheet.