AND gate

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
R_SW1 N5 N3 100u
R_SW2 N5 N4 100u
xU2 0 N4 N2 N5 CS_NORMALLY_OPEN_RELAY PARAMS: CoilInductance=1m CoilResistance=1 OnCurrent=50m OffCurrent=25m
xU3 0 N3 0 N2 CS_NORMALLY_OPEN_RELAY PARAMS: CoilInductance=1m CoilResistance=1 OnCurrent=50m OffCurrent=25m
V_V1 N5 0 dc 0 ac 1 0 distof1 0 0 distof2 0 0 sin ( 0 120 60 0 0 0 )

**************************************************
* Models and supporting definitions follow
**************************************************
.subckt CS_NORMALLY_OPEN_RELAY 1 2 3 4 params: CoilInductance=1m CoilResistance=1 OnCurrent=50m OffCurrent=25m
    LCOIL 1 CI {CoilInductance}
    RCOIL CI CS {CoilResistance}
    VSENSE CS 2 0
    BCTRL CTRL 0 V={abs(I(VSENSE))}
    SCONTACT 3 4 CTRL 0 CS_NORMALLY_OPEN_RELAY_CONTACT
    VSTATEHI RELAY_STATE_HI 0 1
    SSTATE RELAY_STATE RELAY_STATE_HI CTRL 0 CS_NORMALLY_OPEN_RELAY_CONTACT
    RSTATE RELAY_STATE 0 1k
    .model CS_NORMALLY_OPEN_RELAY_CONTACT SW(Ron=1e-8 Roff=1e30 Vt={(OnCurrent+OffCurrent)/2} Vh={(OnCurrent-OffCurrent)/2})
.ends CS_NORMALLY_OPEN_RELAY

**************************************************
* Simulation settings
**************************************************
.tran 333u 0.1 0 333u
.save @r.xU2.rstate[i] @r.xU3.rstate[i]
.end