Aufgabe, d.) 1.)

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
C_C1 N1 0 100n IC=0
R_R1 N6 N1 10K Resistor_1d9c8cf9a__R_R1
X_U1 0 N8 N4 N6 NC_1 N1 N1 N6 555
V_V1 N6 0 dc 5 ac 0 0 distof1 0 0 distof2 0 0
V_V2 N8 0 PWL(0 5 1u 0 500u 0 501u 5 3m 5) R=0
E_VP1 VP1 0 N4 0 1
E_VP2 VP2 0 N1 0 1

**************************************************
* Models and supporting definitions follow
**************************************************
.model Resistor_1d9c8cf9a__R_R1 r(tc1=0 tc2=0 tnom=27)
* Generic 555 functional timing model.
* Trigger has priority over threshold; active-low RESET has highest priority.
* Internal references follow CTRL and the supply relative to VSS.
* Timing/logic model: does not predict supply current, thermal limits or noise.
.subckt 555 VSS TRIG OUT RESET CTRL THRESH DISCH VCC
    RUPPER VCC CTRL 5k
    RMIDDLE CTRL LOWER 5k
    RLOWER LOWER VSS 5k
    BSET SET_LOGIC 0 V = {((V(RESET,VSS)>0.7) && (V(VCC,VSS)>1) && (V(TRIG,VSS)<V(LOWER,VSS))) ? 5 : 0}
    BRESET RESET_LOGIC 0 V = {((V(RESET,VSS)<=0.7) || (V(VCC,VSS)<=1) || ((V(TRIG,VSS)>=V(LOWER,VSS)) && (V(THRESH,VSS)>V(CTRL,VSS)))) ? 5 : 0}
    BEN ENABLE_LOGIC 0 V = 5
    .model CS555_ADC adc_bridge(in_low=2.5 in_high=2.5)
    .model CS555_DAC dac_bridge(out_low=0 out_high=5 out_undef=2.5 t_rise=50n t_fall=50n)
    .model CS555_MEMORY d_srlatch(sr_delay=50n enable_delay=50n set_delay=50n reset_delay=50n rise_delay=50n fall_delay=50n ic=0)
    ASET [SET_LOGIC] [d_s] CS555_ADC
    ARESET [RESET_LOGIC] [d_r] CS555_ADC
    AENABLE [ENABLE_LOGIC] [d_en] CS555_ADC
    AINACTIVE [0] [d_low] CS555_ADC
    ALATCH d_s d_r d_en d_low d_low d_q d_qb CS555_MEMORY
    AQ [d_q] [STATE] CS555_DAC
    AQB [d_qb] [DISCH_STATE] CS555_DAC
    BOUT OUTPUT_DRIVE VSS V = {V(VCC,VSS)*V(STATE)/5}
    ROUT OUTPUT_DRIVE OUT 100
    SDISCH DISCH VSS DISCH_STATE 0 CS555_DISCHARGE
    .model CS555_DISCHARGE SW(Ron=20 Roff=1e12 Vt=2.5 Vh=0)
    RINPUT_TRIG TRIG VSS 1e12
    RINPUT_THRESH THRESH VSS 1e12
    RINPUT_RESET RESET VSS 1e12
.ends 555

**************************************************
* Simulation settings
**************************************************
.options noopalter
.tran 2u 0.003 0 2u uic
.save V(VP1) V(VP2)
.end