3-Input NAND Gate Logic Threshold Sweep

Application

This circuit shows a 3-input NAND gate used as a simple logic-condition detector: the output goes low only when all three inputs are high.

Schematic Organization

Inputs A, B, and C enter from the left. B and C are fixed at 5 V, while A is intended to be swept from 0 V to 5 V. The output drives a 10K load on the right for a direct logic-level check.

Expected Behavior

With VTH set to 2.5 V and VHIGH set to 5 V, Vout remains near 5 V while A is below the threshold. Once A is above 2.5 V and B and C are already high, Vout falls near 0 V.

Suggested Experiments

• Change VTH from 2.5 V to 1.5 V and rerun the sweep.
• Set B or C to 0 V and confirm that Vout remains high across the A sweep.
• Change VHIGH from 5 V to 3.3 V for a lower-voltage logic example.

Featured Component

The 3-input NAND Gate is the featured behavioral equivalent of the Micro-Cap NAND primitive. It keeps the same A, B, C, and OUT external pins while using a supported ngspice expression.