Skip to main content

Task 1

KA

Kay-Klisz

·

Created Oct 12, 2026

·

Updated Oct 13, 2026

Schematic preview for Task 1
Details

Components

5


Schematic

Yes


Simulation

Transient analysis


Copies

Not copied yet

Tags

No tags yet.

About this circuit

The author hasn't added a description yet.

Components used

Components used
5 components
NameManufacturerMPNCountType

DC Voltage Source

Generic

—

1

Official

LED

Generic

—

1

Official

Potentiometer

Generic

—

1

Official

Resistor

Generic

—

1

Official

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
X_D1 N5 0 LED_VIRTUAL_b2f33485 IS=1e-14 N=1 RS=0 CJO=0 M=0.5 VJ=1 BV=1e30 IBV=100p OnCurrent=5m
R_R1 N5 N1 1K Resistor_1d9c8cf9a__R_R1
R_RV1_A 0 N3 'max(1m,100K*25/100)'
R_RV1_B N3 N2 'max(1m,100K*(100-25)/100)'
X_U1 N3 N1 N1 Param3TVIRTUAL_5a7fc2f7 IOS=0 AVOL=200K BW=100meg VOS=0 IBS=0 RI=10meg VOMP=12 VOMN=-12 RO=10
V_V1 N2 0 dc 4 ac 0 0 distof1 0 0 distof2 0 0
E_VP1 VP1 0 N1 0 1

**************************************************
* Models and supporting definitions follow
**************************************************
* LED source-variant replacement with current-sense brightness node
.subckt LED_VIRTUAL_b2f33485 T0 T1 IS=1e-14 N=1 RS=0 CJO=0 M=0.5 VJ=1 BV=1e30 IBV=100p OnCurrent=5m
    DLED T0 SENSE LED_VIRTUAL_b2f33485_DIODE
    .model LED_VIRTUAL_b2f33485_DIODE D(IS={IS} N={N} RS={RS} CJO={CJO} M={M} VJ={VJ} BV={BV} IBV={IBV})
    VSENSE SENSE T1 DC 0
    BLIT lit 0 V = { (i(VSENSE) > {OnCurrent}) ? 1 : ((i(VSENSE) < 0) ? 0 : (i(VSENSE) / {OnCurrent})) }
.ends LED_VIRTUAL_b2f33485
.model Resistor_1d9c8cf9a__R_R1 r(tc1=0 tc2=0 tnom=27)
.model Param3TVIRTUAL_5a7fc2f7_D1 d(n=0.1)
.subckt Param3TVIRTUAL_5a7fc2f7 in_pos in_neg out params: VOS=0 IBS=0 IOS=0 AVOL=200K BW=100M RI=10M RO=10 VOMP=12 VOMN=-12

    * Input Stage: Rin, Ibias, Voffset
    VOS in_pos 4 {VOS}
    Ibias1 4 0 {IBS}
    Ibias2 in_neg 0 {IBS}
    IOS 4 in_neg {IOS/2}
    Rin 4 in_neg {RI}

    *Middle stage: Gain, frequency, voltage limiting
    Bgain 0 6 I={v(4,in_neg)*AVOL/1meg}
    R1 6 0 1meg
    CP1 6 0 {AVOL/(2*3.141592653589793*1meg*BW)}


    Vpos 9 0 {VOMP}
    Dlimit_pos 6 9 Param3TVIRTUAL_5a7fc2f7_D1

    Vneg 10 0 {VOMN}
    Dlimit_neg 10 6 Param3TVIRTUAL_5a7fc2f7_D1


    *Output stage: Buffer, output resistance
    E2 7 0 6 0 1
    Rout 7 out {RO}
.ends

**************************************************
* Simulation settings
**************************************************
.tran 0.000001 100m 0 200p
.save V(VP1) V(X_D1.lit)
.end

Try this circuit yourself

Free to get started. No download — runs in your browser with a full SPICE engine.