Prelab #3-1
XU
xuewang
·
Created Oct 13, 2026
·
Updated Oct 13, 2026

Details
Components
4
Schematic
Yes
Simulation
Transient analysis
Copies
1
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Components used
Components used
4 components
NameManufacturerMPNCountType
OPAMP Ideal rail-to-rail
Analog Devices
OPAMP
1
User
SPICE netlist
* **************************************************
* Generated from CircuitSim Schematic
**************************************************
X_D1 N5 0 LED_VIRTUAL_b2f33485 IS=1e-14 N=1 RS=0 CJO=0 M=0.5 VJ=1 BV=1e30 IBV=100p OnCurrent=5m
R_R1 N1 N3 75K Resistor_1d9c8cf9a__R_R1
R_R2 N3 0 25K Resistor_1d9c8cf9a__R_R2
R_R3 N4 N5 750 Resistor_1d9c8cf9a__R_R3
X_U1 N3 N4 N9 N8 N4 OPAMP_RR
V_V1 N1 0 dc 4 ac 0 0 distof1 0 0 distof2 0 0
V_V2 0 N8 dc 5 ac 0 0 distof1 0 0 distof2 0 0
V_V3 N9 0 dc 5 ac 0 0 distof1 0 0 distof2 0 0
E_VP1 VP1 0 N1 0 1
E_VP2 VP2 0 N3 0 1
E_VP3 VP3 0 N4 0 1
**************************************************
* Models and supporting definitions follow
**************************************************
* LED source-variant replacement with current-sense brightness node
.subckt LED_VIRTUAL_b2f33485 T0 T1 IS=1e-14 N=1 RS=0 CJO=0 M=0.5 VJ=1 BV=1e30 IBV=100p OnCurrent=5m
DLED T0 SENSE LED_VIRTUAL_b2f33485_DIODE
.model LED_VIRTUAL_b2f33485_DIODE D(IS={IS} N={N} RS={RS} CJO={CJO} M={M} VJ={VJ} BV={BV} IBV={IBV})
VSENSE SENSE T1 DC 0
BLIT lit 0 V = { (i(VSENSE) > {OnCurrent}) ? 1 : ((i(VSENSE) < 0) ? 0 : (i(VSENSE) / {OnCurrent})) }
.ends LED_VIRTUAL_b2f33485
.model Resistor_1d9c8cf9a__R_R1 r(tc1=0 tc2=0 tnom=27)
.model Resistor_1d9c8cf9a__R_R2 r(tc1=0 tc2=0 tnom=27)
.model Resistor_1d9c8cf9a__R_R3 r(tc1=0 tc2=0 tnom=27)
* Idealer Rail‑to‑Rail‑OPV mit Sättigung
* Pins: 1 = Non‑Inv (+), 2 = Inv (−), 99 = VCC, 50 = VEE, 3 = Out
.SUBCKT OPAMP_RR 1 2 99 50 3
* Sehr hohe Eingangsimpedanz (DC‑Referenz)
RINP 1 0 1G
RINN 2 0 1G
* Idealer OPV‑Kern: extrem hohe Verstärkung
EGAIN NRAW 0 1 2 1e12
* Begrenzung auf die Rails:
* VOUT = min( VCC , max( VEE , NRAW ) )
* Realisiert über zwei gesteuerte Quellen
* untere Begrenzung (VEE)
ELOW NLOW 0 VALUE = {max(V(NRAW), V(50))}
* obere Begrenzung (VCC)
EHIGH 3 0 VALUE = {min(V(NLOW), V(99))}
.ENDS OPAMP_RR
**************************************************
* Simulation settings
**************************************************
.tran 20u 100m 0 20u
.save V(VP1) V(VP2) V(VP3) V(X_D1.lit)
.endTry this circuit yourself
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