Prelab #3-2 (Copy) (Copy) (Copy)

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
R_R1 N2 N8 1K Resistor_1d9c8cf9a__R_R1
R_R2 N8 N9 50K Resistor_1d9c8cf9a__R_R2
R_R3 N9 0 50K Resistor_1d9c8cf9a__R_R3
R_R4 N9 N10 10K Resistor_1d9c8cf9a__R_R4
R_R5 N10 0 10K Resistor_1d9c8cf9a__R_R5
X_U1 0 N8 N6 N5 N9 OPAMP_RR
V_V1 N2 0 dc 0 ac 1 0 distof1 0 0 distof2 0 0 sin ( 0 150m 1K 0 0 0 )
V_V2 0 N5 dc 5 ac 0 0 distof1 0 0 distof2 0 0
V_V3 N6 0 dc 5 ac 0 0 distof1 0 0 distof2 0 0
E_VP1 VP1 0 N2 0 1
E_VP2 VP2 0 N9 0 1
E_VP3 VP3 0 N10 0 1

**************************************************
* Models and supporting definitions follow
**************************************************
.model Resistor_1d9c8cf9a__R_R1 r(tc1=0 tc2=0 tnom=27)
.model Resistor_1d9c8cf9a__R_R2 r(tc1=0 tc2=0 tnom=27)
.model Resistor_1d9c8cf9a__R_R3 r(tc1=0 tc2=0 tnom=27)
.model Resistor_1d9c8cf9a__R_R4 r(tc1=0 tc2=0 tnom=27)
.model Resistor_1d9c8cf9a__R_R5 r(tc1=0 tc2=0 tnom=27)
* Idealer Rail‑to‑Rail‑OPV mit Sättigung
* Pins: 1 = Non‑Inv (+), 2 = Inv (−), 99 = VCC, 50 = VEE, 3 = Out
.SUBCKT OPAMP_RR 1 2 99 50 3

    * Sehr hohe Eingangsimpedanz (DC‑Referenz)
    RINP 1 0 1G
    RINN 2 0 1G

    * Idealer OPV‑Kern: extrem hohe Verstärkung
    EGAIN NRAW 0 1 2 1e12

    * Begrenzung auf die Rails:
    * VOUT = min( VCC , max( VEE , NRAW ) )
    * Realisiert über zwei gesteuerte Quellen

    * untere Begrenzung (VEE)
    ELOW NLOW 0 VALUE = {max(V(NRAW), V(50))}

    * obere Begrenzung (VCC)
    EHIGH 3 0 VALUE = {min(V(NLOW), V(99))}

.ENDS OPAMP_RR

**************************************************
* Simulation settings
**************************************************
.tran 100u 100m 0
.save V(VP1) V(VP2) V(VP3)
.end