Fully Differential Output Balance Demo
CircuitSim
·
Created May 25, 2026
·
Updated Jun 30, 2026
Details
Components
2
Schematic
Yes
Simulation
Transient analysis
Copies
Not copied yet
About this circuit
Drive a small differential input and compare OUT+ and OUT- around the VOCM setting.
Circuit notes
Fully Differential Output Balance Demo
Application
Drive a small differential input and compare OUT+ and OUT- around the VOCM setting.
Design Context
AD8139 Fully Differential Amplifier is the featured component. The schematic should use realistic support sources, bias paths, loads, and probes for the fully differential amplifier 7pin family.
Expected Behavior
The input or control stimulus should produce a measurable output response while the support rails and reference pins remain at fixed values.
Key Values
- Input/reference level: 200 mV unless the final reviewed schematic calls for a different family-specific level.
- Load: 10K where a voltage output is used.
- Supply: 5 V single-supply or split rails where the selected family requires them.
Suggested Experiments
- Change the input or reference value and compare the output response.
- Adjust the load resistance and observe the output operating point.
- For multi-input families, swap which input is driven and compare the selected output.
Featured Component
AD8139 Fully Differential Amplifier exposes the reviewed fully differential amplifier 7pin pinout imported from the MicroCap source folder.
Components used
Components used
2 components
SPICE netlist
* **************************************************
* Generated from CircuitSim Schematic
**************************************************
* net label +5V joins NET_002::component:u1:VCC net-label-pin:node-1e70eb36-8b0e-484d-ac00-b37c165bf11b:VPLUS::component:node-1e70eb36-8b0e-484d-ac00-b37c165bf11b:VPLUS
* net label -5V joins NET_001::node:junction-4b1d424e-273a-41f6-a4cd-a653e751e026 net-label-pin:node-1e70eb36-8b0e-484d-ac00-b37c165bf11b:VMINUS::component:node-1e70eb36-8b0e-484d-ac00-b37c165bf11b:VMINUS
V_PS1P N8 0 DC 5
V_PS1N N7 0 DC -5
R_RFN N10 N4 1K
R_RFP N10 N2 1K
R_RGN N4 0 1K
R_RGP N2 N1 1K
R_RLN N5 0 100K
R_RLP N10 0 100K
X_U1 N4 N9 N8 N10 N5 N7 N2 AD8139
V_VIN N1 0 SIN(0 0.1 1000 0 0 0 )
V_VOCM N9 0 DC 0
E_VP_OUTN VP_OUTN 0 N5 0 1
E_VP_OUTP VP_OUTP 0 N10 0 1
E_VP_VIN VP_VIN 0 N2 0 1
**************************************************
* Models and supporting definitions follow
**************************************************
* Simulator-supported behavioral equivalent for the fully-differential-amplifier-7pin source macro-model.
.SUBCKT AD8139 INV VOCM VCC VOUTP VOUTN VEE NINV
RBIAS_1_IN_ INV 0 1G
RBIAS_2_VOCM VOCM 0 1G
RBIAS_3_V_ VCC 0 1G
RBIAS_4_OUT_ VOUTP 0 1G
RBIAS_5_OUT_ VOUTN 0 1G
RBIAS_6_V_ VEE 0 1G
RBIAS_7_IN_ NINV 0 1G
EOUTP VOUTP 0 NINV INV 1
EOUTN VOUTN 0 INV NINV 1
.ENDS
**************************************************
* Simulation settings
**************************************************
.tran 0.000009999999999999999 0.004 0
.save V(VP_VIN) V(VP_OUTP) V(VP_OUTN)
.endTry this circuit yourself
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