Fully Differential Output Balance Demo

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
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* net label +5V joins NET_002::component:u1:VCC net-label-pin:node-1e70eb36-8b0e-484d-ac00-b37c165bf11b:VPLUS::component:node-1e70eb36-8b0e-484d-ac00-b37c165bf11b:VPLUS
* net label -5V joins NET_001::node:junction-4b1d424e-273a-41f6-a4cd-a653e751e026 net-label-pin:node-1e70eb36-8b0e-484d-ac00-b37c165bf11b:VMINUS::component:node-1e70eb36-8b0e-484d-ac00-b37c165bf11b:VMINUS
V_PS1P N8 0 DC 5
V_PS1N N7 0 DC -5
R_RFN N10 N4 1K
R_RFP N10 N2 1K
R_RGN N4 0 1K
R_RGP N2 N1 1K
R_RLN N5 0 100K
R_RLP N10 0 100K
X_U1 N4 N9 N8 N10 N5 N7 N2 AD8139
V_VIN N1 0 SIN(0 0.1 1000 0 0 0 )
V_VOCM N9 0 DC 0
E_VP_OUTN VP_OUTN 0 N5 0 1
E_VP_OUTP VP_OUTP 0 N10 0 1
E_VP_VIN VP_VIN 0 N2 0 1

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* Models and supporting definitions follow
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* Simulator-supported behavioral equivalent for the fully-differential-amplifier-7pin source macro-model.
.SUBCKT AD8139 INV VOCM VCC VOUTP VOUTN VEE NINV
    RBIAS_1_IN_ INV 0 1G
    RBIAS_2_VOCM VOCM 0 1G
    RBIAS_3_V_ VCC 0 1G
    RBIAS_4_OUT_ VOUTP 0 1G
    RBIAS_5_OUT_ VOUTN 0 1G
    RBIAS_6_V_ VEE 0 1G
    RBIAS_7_IN_ NINV 0 1G
    EOUTP VOUTP 0 NINV INV 1
    EOUTN VOUTN 0 INV NINV 1
.ENDS

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* Simulation settings
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.tran 0.000009999999999999999 0.004 0
.save V(VP_VIN) V(VP_OUTP) V(VP_OUTN)
.end