New Circuit

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
R_SW1_NC N2 0 100u
R_SW1_NO N2 N3 100G
X_U1 N2 N4 INV VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
vV1 N3 0 dc 5 ac 0 0 distof1 0 0 distof2 0 0
APROBE_DP1 [N2] [d_DP1] AMODEL_DP1
APROBE_DP2 [N4] [d_DP2] AMODEL_DP2

**************************************************
* Models and supporting definitions follow
**************************************************
* Generic digital inverter (NOT gate) with normalized propagation delay
.subckt INV IN OUT VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
    BTARGET TARGET 0 V = {(V(IN) > VTH) ? 0 : VHIGH}
    GDELAY STATE 0 VALUE = {(V(TARGET) > V(STATE)) ? (V(STATE)-V(TARGET))/(((RiseDelay > 1e-15) ? RiseDelay : 1e-15)/(0.69314718056*1e-9)) : (V(STATE)-V(TARGET))/(((FallDelay > 1e-15) ? FallDelay : 1e-15)/(0.69314718056*1e-9))}
    CDELAY STATE 0 1n
    BOUT OUT 0 V = {(V(STATE) >= VHIGH/2) ? VHIGH : 0}
.ends INV
.model AMODEL_DP1 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP2 adc_bridge(in_low=0.8 in_high=2)

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* Simulation settings
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.tran 20u 100m 0 20u
.save time V(N2) V(N4)
.end