c2

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
R_SW1_NC N5 0 100u
R_SW1_NO N5 N1 100G
R_SW2_NC N4 0 100u
R_SW2_NO N4 N1 100G
X_U1 N5 N4 N3 NAND2 VHIGH=5 VTH=2.5
vV1 N1 0 dc 5 ac 0 0 distof1 0 0 distof2 0 0
APROBE_DP1 [N5] [d_DP1] AMODEL_DP1
APROBE_DP2 [N4] [d_DP2] AMODEL_DP2
APROBE_DP4 [N3] [d_DP4] AMODEL_DP4

**************************************************
* Models and supporting definitions follow
**************************************************
* NAND 2-Input gate, ideal behavioral
.subckt NAND2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = {(V(A) > VTH) && (V(B) > VTH) ? 0 : VHIGH}
.ends NAND2
.model AMODEL_DP1 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP2 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP4 adc_bridge(in_low=0.8 in_high=2)

**************************************************
* Simulation settings
**************************************************
.tran 100u 100m 0
.save time V(N5) V(N4) V(N3)
.end