#2

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
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X_74LS08N N1 N4 N3 AND2 VHIGH=5 VTH=2.5
vV1 0 0 dc 5 ac 0 0 distof1 0 0 distof2 0 0
R_X 0 N1 100meg
R_Y 0 N4 100meg
APROBE_DP1 [N3] [d_DP1] AMODEL_DP1
APROBE_DP2 [N1] [d_DP2] AMODEL_DP2
APROBE_DP3 [N1] [d_DP3] AMODEL_DP3

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* Models and supporting definitions follow
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* AND 2-Input gate, ideal behavioral
.subckt AND2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = {((V(A) > VTH) && (V(B) > VTH)) ? VHIGH : 0}
.ends AND2
.model AMODEL_DP1 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP2 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP3 adc_bridge(in_low=0.8 in_high=2)

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* Simulation settings
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.tran 20u 100m 0 20u
.save time V(N3) V(N1)
.end