1_3_2_1_Pt100_Sensor_mit_Brueckenschaltung_ohne_RLtg
FE
feslehrer
·
Created Jun 3, 2026
·
Updated Sep 22, 2026

Details
Components
3
Schematic
Yes
Simulation
Interactive
Copies
Not copied yet
Tags
No tags yet.
About this circuit
The author hasn't added a description yet.
Components used
Components used
3 components
NameManufacturerMPNCountType
OPAMP Ideal rail-to-rail
Analog Devices
OPAMP
2
User
Resistor (EN)
—
—
2
User
SPICE netlist
* **************************************************
* Generated from CircuitSim Schematic
**************************************************
* net label +5V joins NET_005::node:junction-907b973d-d52c-42d8-a933-fc73da8d2b9a NET_022::node:junction-6fba59ce-5cc6-4955-9e97-74386baa963d NET_024::component:node-fb0a5fb6-caac-4372-8086-54fbcf7f7993:99
R_R1 N1 N15 4.7K
R_R3 N1 N3 4.7K
R_R4 N3 0 90.375
R_Re1 N11 N15 100K
R_Re2 N10 N3 100K
R_Rk1 N12 N10 100K
R_Rk2 N7 N6 100K
R_Rq1 0 N11 100K
R_Rq2 N6 0 986
R_RT N14 0 100 temp=0
X_U2 N11 N10 N1 0 N12 OPAMP_RR
X_U3 N12 N6 N1 0 N7 OPAMP_RR
V_Uh N1 0 DC 5
E_Ut Ut 0 N15 0 1
E_U1 U1 0 N12 0 1
E_Uout Uout 0 N7 0 1
E_Ub Ub 0 N3 0 1
V_Im N15 N14 0
**************************************************
* Models and supporting definitions follow
**************************************************
.model Resistor_1d9c8cf9a r(tc1=0 tc2=0 tnom=27)
.model Resistor_1d9c8cf9a r(tc1=3.85m tc2=0 tnom=0)
* Idealer Rail‑to‑Rail‑OPV mit Sättigung
* Pins: 1 = Non‑Inv (+), 2 = Inv (−), 99 = VCC, 50 = VEE, 3 = Out
.SUBCKT OPAMP_RR 1 2 99 50 3
* Sehr hohe Eingangsimpedanz (DC‑Referenz)
RINP 1 0 1G
RINN 2 0 1G
* Idealer OPV‑Kern: extrem hohe Verstärkung
EGAIN NRAW 0 1 2 1e12
* Begrenzung auf die Rails:
* VOUT = min( VCC , max( VEE , NRAW ) )
* Realisiert über zwei gesteuerte Quellen
* untere Begrenzung (VEE)
ELOW NLOW 0 VALUE = {max(V(NRAW), V(50))}
* obere Begrenzung (VCC)
EHIGH 3 0 VALUE = {min(V(NLOW), V(99))}
.ENDS OPAMP_RR
**************************************************
* Simulation settings
**************************************************
.tran 200u 1e12 0 200u
.save V(Ut) V(Ub) V(U1) V(Uout) I(V_Im)
.endTry this circuit yourself
Free to get started. No download — runs in your browser with a full SPICE engine.