New Circuit

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
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X_U1 N5 N5 N4 NAND2 VHIGH=5 VTH=2.5
X_U2 N2 N3 N1 NAND2 VHIGH=5 VTH=2.5
V_U3 N5 0 DC 5
X_U5 N5 N4 N2 NAND2 VHIGH=5 VTH=2.5
X_U6 N4 N5 N3 NAND2 VHIGH=5 VTH=2.5
APROBE_DP1 [N1] [d_DP1] AMODEL_DP1

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* Models and supporting definitions follow
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* NAND 2-Input gate, ideal behavioral
.subckt NAND2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = {(V(A) > VTH) && (V(B) > VTH) ? 0 : VHIGH}
.ends NAND2
.model AMODEL_DP1 adc_bridge(in_low=0.8 in_high=2)

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* Simulation settings
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.tran 20u 100m 0 20u
.save time V(N1)
.end