2_0_DJNF_Lsg

FE

feslehrer

·

Created Jun 5, 2026

·

Updated Sep 22, 2026

Schematic preview for 2_0_DJNF_Lsg
Details

Components

3


Schematic

Yes


Simulation

Interactive


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Components used

Components used
3 components
NameManufacturerMPNCountType

Digital Inverter

Generic

—

5

Official

AND 3-Input

Generic

—

4

Official

OR 4-Input

Generic

—

1

Official

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
X_S1 N3 0 TOGGLEABLE_DIGITAL_CONSTANT state=0 logicLow=0 logicHigh=5
X_S2 N1 0 TOGGLEABLE_DIGITAL_CONSTANT state=1 logicLow=0 logicHigh=5
X_S3 N2 0 TOGGLEABLE_DIGITAL_CONSTANT state=1 logicLow=0 logicHigh=5
X_U12 N3 N1 N2 N9 AND3 VHIGH=5 VTH=2.5
X_U17 N3 N10 INV VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
X_U18 N9 N4 N12 N5 N13 OR4 VHIGH=5 VTH=2.5
X_U19 N10 N1 N11 N4 AND3 VHIGH=5 VTH=2.5
X_U20 N6 N1 N2 N12 AND3 VHIGH=5 VTH=2.5
X_U21 N3 N7 N8 N5 AND3 VHIGH=5 VTH=2.5
X_U22 N2 N11 INV VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
X_U23 N3 N6 INV VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
X_U24 N1 N7 INV VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
X_U25 N2 N8 INV VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
APROBE_Q1 [N13] [d_Q1] AMODEL_Q1

**************************************************
* Models and supporting definitions follow
**************************************************
* Toggleable digital constant logic-level source
.subckt TOGGLEABLE_DIGITAL_CONSTANT OUT GND PARAMS: state=0 logicLow=0 logicHigh=5
    BOUT OUT GND V = {logicLow+(logicHigh-logicLow)*state}
.ends TOGGLEABLE_DIGITAL_CONSTANT
* AND 3-Input gate, ideal behavioral
.subckt AND3 A B C OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = {((V(A) > VTH) && (V(B) > VTH) && (V(C) > VTH)) ? VHIGH : 0}
.ends AND3
* Generic digital inverter (NOT gate) with normalized propagation delay
.subckt INV IN OUT VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
    BTARGET TARGET 0 V = {(V(IN) > VTH) ? 0 : VHIGH}
    GDELAY STATE 0 VALUE = {(V(TARGET) > V(STATE)) ? (V(STATE)-V(TARGET))/(((RiseDelay > 1e-15) ? RiseDelay : 1e-15)/(0.69314718056*1e-9)) : (V(STATE)-V(TARGET))/(((FallDelay > 1e-15) ? FallDelay : 1e-15)/(0.69314718056*1e-9))}
    CDELAY STATE 0 1n
    BOUT OUT 0 V = {(V(STATE) >= VHIGH/2) ? VHIGH : 0}
.ends INV
* OR 4-Input gate, ideal behavioral
.subckt OR4 A B C D OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = {((V(A) > VTH) || (V(B) > VTH) || (V(C) > VTH) || (V(D) > VTH)) ? VHIGH : 0}
.ends OR4
.model AMODEL_Q1 adc_bridge(in_low=3.3 in_high=3.3)

**************************************************
* Simulation settings
**************************************************
.tran 2m 1e12 0 2m
.save time V(N13)
.end

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