2_0_DJNF_Lsg

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
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X_S1 N5 0 TOGGLEABLE_DIGITAL_CONSTANT state=1 logicLow=0 logicHigh=5
X_S2 N7 0 TOGGLEABLE_DIGITAL_CONSTANT state=0 logicLow=0 logicHigh=5
X_S3 N8 0 TOGGLEABLE_DIGITAL_CONSTANT state=1 logicLow=0 logicHigh=5
X_U10 N1 N4 N3 N2 N9 OR4 VHIGH=5 VTH=2.5
X_U11 N5 N6 NOT VHIGH=5 VTH=2.5
X_U13 N8 N10 NOT VHIGH=5 VTH=2.5
X_U14 N5 N11 NOT VHIGH=5 VTH=2.5
X_U15 N7 N12 NOT VHIGH=5 VTH=2.5
X_U16 N8 N13 NOT VHIGH=5 VTH=2.5
X_U18 N5 N7 N8 N1 AND3 VHIGH=5 VTH=2.5
X_U19 N6 N7 N10 N4 AND3 VHIGH=5 VTH=2.5
X_U20 N11 N7 N8 N3 AND3 VHIGH=5 VTH=2.5
X_U21 N5 N12 N13 N2 AND3 VHIGH=5 VTH=2.5
APROBE_Q1 [N9] [d_Q1] AMODEL_Q1

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* Models and supporting definitions follow
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* Toggleable digital constant logic-level source
.subckt TOGGLEABLE_DIGITAL_CONSTANT OUT GND PARAMS: state=0 logicLow=0 logicHigh=5
    BOUT OUT GND V = {logicLow+(logicHigh-logicLow)*state}
.ends TOGGLEABLE_DIGITAL_CONSTANT
* 4-input OR gate, ideal behavioral
.subckt OR4 A B C D OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = { (V(A) > VTH || V(B) > VTH || V(C) > VTH || V(D) > VTH) ? VHIGH : 0 }
.ends OR4
* NOT gate, ideal, no supply pins
.subckt NOT A OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = { (V(A) > VTH) ? 0 : VHIGH }
.ends NOT
* 3-input AND gate, ideal, no supply pins
.subckt AND3 A B C OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = { (V(A) > VTH && V(B) > VTH && V(C) > VTH) ? VHIGH : 0 }
.ends AND3
.model AMODEL_Q1 adc_bridge(in_low=3.3 in_high=3.3)

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* Simulation settings
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.op
.end