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vishwasnarayan2345
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Created Nov 1, 2026
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Updated Nov 1, 2026
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* CMOS INVERTER VDD VDD 0 DC 5 VIN IN 0 PULSE(0 5 0 1n 1n 5u 10u) .model NMOD NMOS (LEVEL=1 VTO=0.7 KP=120u GAMMA=0.4 PHI=0.7 LAMBDA=0.02) .model PMOD PMOS (LEVEL=1 VTO=-0.7 KP=50u GAMMA=0.4 PHI=0.7 LAMBDA=0.02) M1 OUT IN VDD VDD PMOD W=10u L=1u M2 OUT IN 0 0 NMOD W=5u L=1u CLOAD OUT 0 10p .tran 0 50u 0 1n .meas TRAN TPHL TRIG V(IN) VAL=2.5 RISE=1 TARG V(OUT) VAL=2.5 FALL=1 .meas TRAN TPLH TRIG V(IN) VAL=2.5 FALL=1 TARG V(OUT) VAL=2.5 RISE=1 .meas TRAN PAVG AVG -V(VDD)*I(VDD) FROM=0 TO=50u .end
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