New Circuit

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
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R_R1 N2 0 1K
X_U1 N3 N2 PWM_4065ea6a Frequency=10K OutputVoltage=5 TriangleMin=0 TriangleMax=1
V_V1 N4 0 dc 5 ac 0 0 distof1 0 0 distof2 0 0
E_VP1 VP1 0 N2 0 1
E_VP2 VP2 0 N4 0 1

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* Models and supporting definitions follow
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.model Resistor_1d9c8cf9a r(tc1=0 tc2=0 tnom=27)
.subckt PWM_4065ea6a in out params: Frequency=10K TriangleMin=0 TriangleMax=1 OutputVoltage=5
    * The small phase offset and plateaus avoid terminal-timestep events while preserving a 99.8% linear triangle period.
    Vtriangle triangle 0 PULSE({TriangleMin} {TriangleMax} {0.0001/Frequency} {0.499/Frequency} {0.499/Frequency} {0.001/Frequency} {1/Frequency})
    Bout out 0 V={(V(in)>V(triangle)) ? OutputVoltage : 0}
.ends

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* Simulation settings
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.tran 2u 1e12 0 2u
.save V(VP1) V(VP2)
.end