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SPICE netlist

* ========================================================
* Graph (b): CSB-SA With 200mV VTH Mismatch (Read Failure)
* Final Fixed Web-SPICE Netlist
* ========================================================
.option post=1 nomod
.param VDD_VAL=1.0V VG_CLAMP_VAL=0.8V

* 1. 65nm CMOS Models 
.model NMOS NMOS (LEVEL=1 VTO=0.35 KP=200u LAMBDA=0.01)
.model PMOS PMOS (LEVEL=1 VTO=-0.35 KP=200u LAMBDA=0.01)
.model PMOS_M1 PMOS (LEVEL=1 VTO=-0.10 KP=200u LAMBDA=0.01)

* 2. Power Supplies (VVSS removed, GND replaced with 0)
VVDD VDD 0 DC VDD_VAL
VVG VG_CLAMP 0 DC VG_CLAMP_VAL

* 3. Control Signals (TR=0.1ns, TF=0.1ns)
VPRE PRE 0 PULSE(1.0V 0V 10ns 0.1ns 0.1ns 10ns 20ns)
VAMP AMP 0 DC 0V

* 4. Memory Cell Resistance (State 1: RCELL = 6.0k > RREF = 4.5k)
RCELL BL  0 6.0k
RREF  DBL 0 4.5k
CBL   BL  0 100fF
CDBL  DBL 0 100fF

* 5. Degeneration pMOS (M7, M8 Gate connected to 0)
M7 N_M1 0 VDD VDD PMOS W=1.0u L=0.1u
M8 N_M2 0 VDD VDD PMOS W=1.0u L=0.1u

* 6. Load pMOS Transistors (M1 uses PMOS_M1 with VTO=-0.10V)
M1 SA1 G1 N_M1 VDD PMOS_M1 W=4.0u L=0.1u
M2 SA2 G2 N_M2 VDD PMOS W=4.0u L=0.1u

* 7. Diode Connection Switches (S3, S4)
M9  SA1 PRE G1 0 NMOS W=2.0u L=0.06u
M10 SA2 PRE G2 0 NMOS W=2.0u L=0.06u

* 8. pMOS Capacitors (C1, C2)
M5 G2 SA1 SA1 VDD PMOS W=4.0u L=0.2u
M6 G1 SA2 SA2 VDD PMOS W=4.0u L=0.2u

* 9. Pass Switches (S1, S2)
M11 SA1 PRE N_BL1 0 NMOS W=2.0u L=0.06u
M12 SA2 PRE N_BL2 0 NMOS W=2.0u L=0.06u

* 10. Bit-Line Clamp nMOS (M3, M4)
M3 N_BL1 VG_CLAMP BL  0 NMOS W=4.0u L=0.1u
M4 N_BL2 VG_CLAMP DBL 0 NMOS W=4.0u L=0.1u

* 11. Initial Convergence Conditions
.ic V(SA1)=0.1V V(SA2)=0.1V V(BL)=0.1V V(DBL)=0.1V

* 12. Standard Node Prints (Replaced .probe with .print)
.print tran v(sa1) v(sa2) v(pre) v(amp)

* 13. Transient Analysis
.tran 0.01ns 20ns
.end