Inverter Logic-Level Check

Application

This circuit uses the inverter as a single-input logic stage. The input source provides a high level, and the output is measured after inversion.

Schematic Organization

The input source is on the left, the featured inverter is centered, and the output drives a light 10K load on the right. A digital probe sits directly on the output wire.

Expected Behavior

With A held at 5 V and the input threshold at 2.5 V, Y should read as logic low. Setting A to 0 V should make Y read high.

Suggested Experiments

Change VA between 0 V and 5 V and rerun the transient simulation. Then try changing the rise and fall delay values to see how they affect edge timing in switched examples.

Featured Component

The featured component keeps the imported A-to-Y pin arrangement while exposing timing parameters for later transient experiments.