HalfWaveControlledRectifierForResistenceLoad (Copy)

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
C_C1 N5 0 1p IC=0
C_C2 N10 0 8.333n IC=0
X_D2 N4 N11 0 MCR8SNON_ef049519
R_LAMP1 N2 N3 484
R_R2 N4 N5 31meg Resistor_1d9c8cf9a__R_R2
R_R3 N6 N2 100K Resistor_1d9c8cf9a__R_R3
R_R4 N6 0 3.3K Resistor_1d9c8cf9a__R_R4
R_R5 N9 N11 1 Resistor_1d9c8cf9a__R_R5
R_R6 N8 0 1G Resistor_1d9c8cf9a__R_R6
R_RV1_A N10 N8 'max(1m,100K*6/100)'
R_RV1_B N8 N8 'max(1m,100K*(100-6)/100)'
X_U1 N6 0 N7 0 N8 OPAMP_RR
V_V1 N2 0 dc 0 ac 1 0 distof1 0 0 distof2 0 0 sin ( 0 311.127 60 0 0 0 )
vV2 N7 0 dc 5 ac 0 0 distof1 0 0 distof2 0 0
E_VP1 VP1 0 N2 N4 1
E_VP2 VP2 0 N4 0 1
E_VP3 VP3 0 N8 0 1
E_VP4 VP4 0 N10 0 1
V_IP1 N3 N4 0
V_IP2 N10 N9 0

**************************************************
* Models and supporting definitions follow
**************************************************
.MODEL MCR8SNON_ef049519_Vswitch SW(Ron={(1.25-0.7)/16} Roff={960*960/(1.25*0.5m)} Vt={(5.0+1.5)/2} Vh={(5.0-1.5)*0.499})
.MODEL MCR8SNON_ef049519_Dgk D (Is=1E-16 Cjo=50pf Rs=5)
.MODEL MCR8SNON_ef049519_Dseries D (Is=1E-14)
.MODEL MCR8SNON_ef049519_Delay D (Is=1E-12 Cjo=5pf Rs=0.01)
.MODEL MCR8SNON_ef049519_Dkarev D (Is=1E-10 Cjo=5pf Rs=0.01)
.MODEL MCR8SNON_ef049519_Dakfwd D (Is=4E-11 Cjo=5pf)
.MODEL MCR8SNON_ef049519_Dbreak D (Ibv=1E-7 Bv={1.1*960} Cjo=5pf Rs=0.5)
.subckt MCR8SNON_ef049519 anode gate cathode PARAMS:
    **************************************
    * Model Generated by CZ LAB *
    * August 27, 2001 *
    * Copyright(c) On Semiconductor *
    * All Rights Reserved *
    *Commercial Use or Resale Restricted *
    **************************************
    *Silicon Controlled Rectifier
    *MODEL FORMAT: PSpice
    .param Vdrm=960 Vrrm=960 Idrm=10u
    .param Ih=0.5m dVdt=1.5e7
    .param Igt=0.025m Vgt=0.7
    * Vgt must be greater than 0.65
    .param Vtm=1.25 Itm=16
    .param Ton=2u Toff=15u
    * Where:
    * Vdrm => Forward breakover voltage
    * Vrrm => Reverse breakdown voltage
    * Idrm => Peak blocking current
    * Ih => Holding current
    * dVdt => Critical value for dV/dt triggering
    * Igt => Gate trigger current
    * Vgt => Gate trigger voltage
    * Vtm => On-state voltage
    * Itm => On-state current
    * Ton => Turn-on time
    * Toff => Turn-off time
    *-------------------------------------------------------------------------------
    * Library of Thyristor (SCR and Triac) models
    * This is a reduced version of MicroSim's Thyristor components library.
    * You are welcome to make as many copies of it as you find convenient.
    * Library of SCR models
    * NOTE: This library requires the "Analog Behavioral Modeling"
    * option available with PSpice. A model developed without
    * Behavioral Modeling was found to be very slow and not
    * very robust.
    * This macromodel uses a controlled switch as the basic SCR
    * structure. In all cases, the designer should use
    * the manufacturer's data book for actual part selection.
    * The required parameters were derived from data sheet (Motorola)
    * information on each part. When available, only "typical"
    * parameters are used (except for Idrm which is always
    * a "max" value). If a "typical" parameter is not available,
    * a "min" or "max" value may be used in which case a comment is
    * made in the library.
    * The SCRs are modeled at room temperature and do not track
    * changes with temperature. Note that Vdrm is specified by the
    * manufacturer as valid over a temperature range. Also, in
    * nearly all cases, dVdt and Toff are specified by the
    * manufacturer at approximately 100 degrees C. This results in a
    * model which is somewhat "conservative" for a room temperature
    * model.
    * The parameter dVdt (when available from the date sheet) is used
    * to model the Critical Rate of Rise of Off-State Voltage. If
    * not specified, dVdt is defaulted to 1000 V/microsecond.
    * A side effect of this model is that the turn-on current, Ion,
    * is determined by Vtm/(Ih*Vdrm). Vtm is also used as the
    * holding voltage.
    * Main conduction path
    Scr anode anode0 control 0 MCR8SNON_ef049519_Vswitch ; controlled switch
    Dak1 anode0 anode2 MCR8SNON_ef049519_Dakfwd OFF ; SCR is initially off
    Dka cathode anode0 MCR8SNON_ef049519_Dkarev OFF
    VIak anode2 cathode ; current sensor
    * dVdt Turn-on
    Emon dvdt0 0 TABLE {v(anode,cathode)} (0 0) (2000 2000)
    CdVdt dvdt0 dvdt1 100p ; displacement current
    Rdlay dvdt1 dvdt2 1k
    VdVdt dvdt2 cathode DC 0.0
    EdVdt condvdt 0 TABLE {i(vdVdt)-100p*dVdt} (0 0 ) (.1m 10)
    RdVdt condvdt 0 1meg
    * Gate
    Rseries gate gate1 {(Vgt-0.65)/Igt}
    Rshunt gate1 gate2 {0.65/Igt}
    Dgkf gate1 gate2 MCR8SNON_ef049519_Dgk
    VIgf gate2 cathode ; current sensor
    * Gate Turn-on
    Egate1 gate4 0 TABLE {i(Vigf)-0.95*Igt} (0 0) (1m 10)
    Rgate1 gate4 0 1meg
    Egon1 congate 0 TABLE {v(gate4)*v(anode,cathode)} (0 0) (10 10)
    Rgon1 congate 0 1meg
    * Main Turn-on
    EItot Itot 0 TABLE {i(VIak)+5E-5*i(VIgf)/Igt} (0 0) (2000 2000)
    RItot Itot 0 1meg
    Eprod prod 0 TABLE {v(anode,cathode)*v(Itot)} (0 0) (1 1)
    Rprod prod 0 1meg
    Elin conmain 0 TABLE
    + {10*(v(prod) - (Vtm*Ih))/(Vtm*Ih)} (0 0) (2 10)
    Rlin conmain 0 1meg
    * Turn-on/Turn-off control
    Eonoff contot 0 TABLE
    + {v(congate)+v(conmain)+v(condvdt)} (0 0) (10 10)
    * Turn-on/Turn-off delays
    Rton contot dlay1 825
    Dton dlay1 control MCR8SNON_ef049519_Delay
    Rtoff contot dlay2 {290*Toff/Ton}
    Dtoff control dlay2 MCR8SNON_ef049519_Delay
    Cton control 0 {Ton/454}
    * Reverse breakdown
    Dbreak anode break1 MCR8SNON_ef049519_Dbreak
    Dbreak2 cathode break1 MCR8SNON_ef049519_Dseries
    * Controlled switch model
    * Diodes
    * Allow the gate to float if required
    Rfloat gate cathode 1e10
.ENDS
*$
.model Resistor_1d9c8cf9a__R_R2 r(tc1=0 tc2=0 tnom=27)
.model Resistor_1d9c8cf9a__R_R3 r(tc1=0 tc2=0 tnom=27)
.model Resistor_1d9c8cf9a__R_R4 r(tc1=0 tc2=0 tnom=27)
.model Resistor_1d9c8cf9a__R_R5 r(tc1=0 tc2=0 tnom=27)
.model Resistor_1d9c8cf9a__R_R6 r(tc1=0 tc2=0 tnom=27)
* Idealer Rail‑to‑Rail‑OPV mit Sättigung
* Pins: 1 = Non‑Inv (+), 2 = Inv (−), 99 = VCC, 50 = VEE, 3 = Out
.SUBCKT OPAMP_RR 1 2 99 50 3

    * Sehr hohe Eingangsimpedanz (DC‑Referenz)
    RINP 1 0 1G
    RINN 2 0 1G

    * Idealer OPV‑Kern: extrem hohe Verstärkung
    EGAIN NRAW 0 1 2 1e12

    * Begrenzung auf die Rails:
    * VOUT = min( VCC , max( VEE , NRAW ) )
    * Realisiert über zwei gesteuerte Quellen

    * untere Begrenzung (VEE)
    ELOW NLOW 0 VALUE = {max(V(NRAW), V(50))}

    * obere Begrenzung (VCC)
    EHIGH 3 0 VALUE = {min(V(NLOW), V(99))}

.ENDS OPAMP_RR

**************************************************
* Simulation settings
**************************************************
.tran 333u 0.0666666 0 333u uic
.save V(VP1) V(VP2) V(VP3) V(VP4) I(V_IP1) I(V_IP2) @R_LAMP1[i]
.end