Digital Demo

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SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
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X_CLK_0 N1 0 CLOCK DUTY=50 VHIGH=5 VLOW=0 PERIOD=1m
X_CLK_1 N2 0 CLOCK DUTY=50 VHIGH=5 VLOW=0 PERIOD=2m
X_U3 N1 N2 N4 AND2 VHIGH=5 VTH=2.5
X_U4 N1 N2 N5 NAND2 VHIGH=5 VTH=2.5
X_U5 N1 N2 N6 OR2 VHIGH=5 VTH=2.5
X_U6 N2 N2 N7 NOR2 VHIGH=5 VTH=2.5
X_U7 N1 N2 N8 XOR2 VHIGH=5 VTH=2.5
APROBE_DP1 [N1] [d_DP1] AMODEL_DP1
APROBE_DP2 [N2] [d_DP2] AMODEL_DP2
APROBE_DP3 [N4] [d_DP3] AMODEL_DP3
APROBE_DP4 [N5] [d_DP4] AMODEL_DP4
APROBE_DP5 [N6] [d_DP5] AMODEL_DP5
APROBE_DP6 [N7] [d_DP6] AMODEL_DP6
APROBE_DP7 [N8] [d_DP7] AMODEL_DP7

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* Models and supporting definitions follow
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* Clock generator with duty cycle in percent (0–100)
.subckt CLOCK OUT GND VHIGH=5 VLOW=0 PERIOD=1m DUTY=50
    .param DUTY_FRAC = { DUTY / 100 } * Convert percent to fraction
    .param TON  = { PERIOD * DUTY_FRAC }
    VCLK OUT 0 PULSE( VLOW VHIGH 0 1n 1n {TON} {PERIOD} )
.ends CLOCK
* 2-input AND gate, ideal, no supply pins
.subckt AND2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = { (V(A) > VTH && V(B) > VTH) ? VHIGH : 0 }
.ends AND2
* 2-input NAND gate, ideal behavioral
.subckt NAND2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = { (V(A) > VTH && V(B) > VTH) ? 0 : VHIGH }
.ends NAND2
* 2-input OR gate, ideal behavioral
.subckt OR2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = { (V(A) > VTH || V(B) > VTH) ? VHIGH : 0 }
.ends OR2
* 2-input NOR gate, ideal behavioral
.subckt NOR2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = { (V(A) > VTH || V(B) > VTH) ? 0 : VHIGH }
.ends NOR2
* 2-input XOR gate, ideal behavioral
.subckt XOR2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = { ((V(A) > VTH) != (V(B) > VTH)) ? VHIGH : 0 }
.ends XOR2
.model AMODEL_DP1 adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_DP2 adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_DP3 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP4 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP5 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP6 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP7 adc_bridge(in_low=0.8 in_high=2)

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* Simulation settings
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.tran .000001 0.004 0
.save time
.end