74LS93 hexadecimal count display

This application note shows the 74LS93N 4-Bit Binary Counter driving a dynamic hexadecimal seven-segment display. It is a compact way to explore ripple counting, frequency division, and binary-to-hexadecimal display behavior.

What to expect

• The interactive simulation starts automatically and the display begins at 0.
• At about 1 second, the display advances to 1, then increments once per second.
• The sequence is 0, 1, 2, …, 9, A, b, C, d, E, F, then wraps back to 0.
• Stop and restart the simulation to begin again from zero.

How it works

• CLK1 is configured for 1 Hz, 50% duty cycle, and a 0.5-second startup delay. This places the first active count transition at roughly one second.
• QA is fed back to INB through matching QA net labels, cascading the divide-by-two stage into the remaining three counter stages.
• R01 and R02 are held at ground, so asynchronous reset stays inactive.
• Matching QA–QD labels carry the four counter bits to display inputs A–D. A is the least-significant bit and D is the most-significant bit.
• Four 10 kΩ loads provide a DC reference for the mixed-signal counter outputs; the display inputs are intentionally high impedance.

The letter shapes use conventional seven-segment approximations: lowercase b and d distinguish those values from 8 and 0.

Try it

• Change CLK1 Frequency to 2 Hz and confirm that the display counts twice as fast.
• Change CLK1 Delay to see how the first count transition moves.
• Temporarily drive both reset inputs high to observe the asynchronous clear behavior, then return them low to resume counting.