1_2_4_Summierverstärker

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
R_P1_A 0 N18 'max(1m,1K*13/100)'
R_P1_B N18 N7 'max(1m,1K*(100-13)/100)'
R_Re1 N13 N8 10k
R_Re12 N17 N15 10k
R_Re2 N12 N8 10k
R_Re22 N18 N15 10K
R_Rk N8 N10 30K
R_Rk2 N15 N16 10k
X_U1 0 N8 N9 Param3TVIRTUAL_5a7fc2f7 IOS=0 AVOL=200k BW=100meg VOS=0 IBS=0 RI=10meg VOMP=15 VOMN=-15 RO=10
X_U2 0 N15 N16 Param3TVIRTUAL_5a7fc2f7 IOS=0 AVOL=200k BW=100meg VOS=0 IBS=0 RI=10meg VOMP=15 VOMN=-15 RO=10
V_Ue1 N14 0 dc 1 ac 0 0 distof1 0 0 distof2 0 0
V_Ue12 N17 0 dc 0 ac 1 0 distof1 0 0 distof2 0 0 sin ( 0 2 1k 0 0 0 )
V_Ue2 N11 0 dc 2 ac 0 0 distof1 0 0 distof2 0 0
V_Ue22 N7 0 dc -15 ac 0 0 distof1 0 0 distof2 0 0
E_Ua Ua 0 N9 0 1
E_Ue1 Ue1 0 N17 0 1
E_VP1 VP1 0 N18 0 1
E_VP2 VP2 0 N16 0 1
V_IP1 N10 N9 0
V_Ie2 N11 N12 0
V_Ie1 N14 N13 0

**************************************************
* Models and supporting definitions follow
**************************************************
.model Resistor_1d9c8cf9a r(tc1=0 tc2=0 tnom=27)
.model Param3TVIRTUAL_5a7fc2f7_D1 d(n=0.1)
.subckt Param3TVIRTUAL_5a7fc2f7 in_pos in_neg out params: VOS=0 IBS=0 IOS=0 AVOL=200K BW=100M RI=10M RO=10 VOMP=12 VOMN=-12

    * Input Stage: Rin, Ibias, Voffset
    VOS in_pos 4 {VOS}
    Ibias1 4 0 {IBS}
    Ibias2 in_neg 0 {IBS}
    IOS 4 in_neg {IOS/2}
    Rin 4 in_neg {RI}

    *Middle stage: Gain, frequency, voltage limiting
    Bgain 0 6 I={v(4,in_neg)*AVOL/1meg}
    R1 6 0 1meg
    CP1 6 0 {AVOL/(2*3.141592653589793*1meg*BW)}


    Vpos 9 0 {VOMP}
    Dlimit_pos 6 9 Param3TVIRTUAL_5a7fc2f7_D1

    Vneg 10 0 {VOMN}
    Dlimit_neg 10 6 Param3TVIRTUAL_5a7fc2f7_D1


    *Output stage: Buffer, output resistance
    E2 7 0 6 0 1
    Rout 7 out {RO}
.ends

**************************************************
* Simulation settings
**************************************************
.options rshunt=1e12
.tran 10u 1e12 0 10u
.save V(Ue1) V(VP1) V(Ua) V(VP2) I(V_Ie2) I(V_Ie1) I(V_IP1)
.end