6_1_1_Einfaches_RS_Flipflop

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
V_Reset N3 0 DC 0
V_Set N2 0 DC 0
X_U10 N1 N8 N9 AND2 VHIGH=5 VTH=2.5
X_U11 N2 N9 N8 OR2 VHIGH=5 VTH=2.5
X_U12 N3 N1 INV VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
X_U13 N2 N4 INV VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
X_U14 N3 N5 INV VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
X_U8 N4 N7 N6 NAND2 VHIGH=5 VTH=2.5
X_U9 N6 N5 N7 NAND2 VHIGH=5 VTH=2.5
APROBE_S [N2] [d_S] AMODEL_S
APROBE_R [N3] [d_R] AMODEL_R
APROBE_DP1 [N8] [d_DP1] AMODEL_DP1
APROBE_DP2 [N6] [d_DP2] AMODEL_DP2
APROBE_DP3 [N7] [d_DP3] AMODEL_DP3

**************************************************
* Models and supporting definitions follow
**************************************************
* AND 2-Input gate, ideal behavioral
.subckt AND2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = {((V(A) > VTH) && (V(B) > VTH)) ? VHIGH : 0}
.ends AND2
* OR 2-Input gate, ideal behavioral
.subckt OR2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = {(V(A) > VTH) || (V(B) > VTH) ? VHIGH : 0}
.ends OR2
* Generic digital inverter (NOT gate) with normalized propagation delay
.subckt INV IN OUT VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
    BTARGET TARGET 0 V = {(V(IN) > VTH) ? 0 : VHIGH}
    GDELAY STATE 0 VALUE = {(V(TARGET) > V(STATE)) ? (V(STATE)-V(TARGET))/(((RiseDelay > 1e-15) ? RiseDelay : 1e-15)/(0.69314718056*1e-9)) : (V(STATE)-V(TARGET))/(((FallDelay > 1e-15) ? FallDelay : 1e-15)/(0.69314718056*1e-9))}
    CDELAY STATE 0 1n
    BOUT OUT 0 V = {(V(STATE) >= VHIGH/2) ? VHIGH : 0}
.ends INV
* NAND 2-Input gate, ideal behavioral
.subckt NAND2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = {(V(A) > VTH) && (V(B) > VTH) ? 0 : VHIGH}
.ends NAND2
.model AMODEL_S adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_R adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_DP1 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP2 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP3 adc_bridge(in_low=0.8 in_high=2)

**************************************************
* Simulation settings
**************************************************
.options rshunt=1e12
.tran 0.01 1e12 0 0.0001
.save time V(N2) V(N3) V(N8) V(N6) V(N7)
.end