6_1_1_Einfaches_RS_Flipflop

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
V_Reset N4 0 DC 0
V_Set N3 0 DC 0
X_U1 N3 N2 N9 DigitalOR2_5fae4f37 RiseDelay=1n FallDelay=1n
X_U10 N3 N4 N10 N11 RS_LATCH
X_U2 N1 N9 N2 DigitalAND2_5fae4f37 RiseDelay=1e-9 FallDelay=1e-9
X_U3 N4 N1 DigitalInverter_fa18a92b RiseDelay=1e-9 FallDelay=1e-9
X_U6 N3 N5 DigitalInverter_fa18a92b RiseDelay=1e-9 FallDelay=1e-9
X_U7 N4 N6 DigitalInverter_fa18a92b RiseDelay=1e-9 FallDelay=1e-9
X_U8 N5 N8 N7 NAND2 VHIGH=5 VTH=2 RiseDelay=1n FallDelay=1n
X_U9 N7 N6 N8 NAND2 VHIGH=5 VTH=2 RiseDelay=1n FallDelay=1n
APROBE_S [N3] [d_S] AMODEL_S
APROBE_R [N4] [d_R] AMODEL_R
APROBE_DP1 [N9] [d_DP1] AMODEL_DP1
APROBE_DP2 [N7] [d_DP2] AMODEL_DP2
APROBE_DP3 [N8] [d_DP3] AMODEL_DP3
APROBE_DP4 [N10] [d_DP4] AMODEL_DP4
APROBE_DP5 [N11] [d_DP5] AMODEL_DP5

**************************************************
* Models and supporting definitions follow
**************************************************
.model DigitalOR2_5fae4f37_DigitalOR25fae4f37A2D adc_bridge(in_low=2.5 in_high=2.5)
.model DigitalOR2_5fae4f37_DigitalOR25fae4f37D2A dac_bridge(out_low=0 out_high=5 out_undef=2.5)
* 2-input OR gate with analog logic bridges and propagation delay
.subckt DigitalOR2_5fae4f37 T0 T1 T2 params: RiseDelay=1e-9 FallDelay=1e-9
    .model DigitalOR2_5fae4f37_DigitalOR25fae4f37CORE d_or(rise_delay={RiseDelay} fall_delay={FallDelay})
    AT0_IN [T0] [d_t0] DigitalOR2_5fae4f37_DigitalOR25fae4f37A2D
    AT1_IN [T1] [d_t1] DigitalOR2_5fae4f37_DigitalOR25fae4f37A2D
    AOR [d_t0 d_t1] d_out DigitalOR2_5fae4f37_DigitalOR25fae4f37CORE
    AOUT [d_out] [T2] DigitalOR2_5fae4f37_DigitalOR25fae4f37D2A
.ends DigitalOR2_5fae4f37
* ---------------------------------------------------------
* Setzdominantes RS-Flipflop (NOR-Latch)
* Pins: S  R  Q  Qbar
* ---------------------------------------------------------
.subckt RS_LATCH S R Q Q_N

    X1 Q     S     Q_N  NOR2
    X2 Qbar  R     Q    NOR2

.ends RS_LATCH

.subckt NOR2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = {(V(A) > VTH || V(B) > VTH) ? 0 : VHIGH}
.ends NOR2
* 2-input AND gate with analog logic bridges and propagation delay
.subckt DigitalAND2_5fae4f37 T0 T1 T2 RiseDelay=1e-9 FallDelay=1e-9
    .model DigitalAND2_5fae4f37_A2D adc_bridge(in_low=2.5 in_high=2.5)
    .model DigitalAND2_5fae4f37_D2A dac_bridge(out_low=0 out_high=5 out_undef=2.5)
    .model DigitalAND2_5fae4f37_CORE d_and(rise_delay={RiseDelay} fall_delay={FallDelay})
    AA_IN [T0] [d_t0] DigitalAND2_5fae4f37_A2D
    AT1_IN [T1] [d_t1] DigitalAND2_5fae4f37_A2D
    AAND [d_t0 d_t1] d_out DigitalAND2_5fae4f37_CORE
    AOUT [d_out] [T2] DigitalAND2_5fae4f37_D2A
.ends DigitalAND2_5fae4f37
* Inverter source-variant replacement with analog logic bridges
.subckt DigitalInverter_fa18a92b T0 T1 RiseDelay=1e-9 FallDelay=1e-9
    .model DigitalInverter_fa18a92b_A2D adc_bridge(in_low=2.5 in_high=2.5)
    .model DigitalInverter_fa18a92b_D2A dac_bridge(out_low=0 out_high=5 out_undef=2.5)
    .model DigitalInverter_fa18a92b_CORE d_inverter(rise_delay={RiseDelay} fall_delay={FallDelay})
    AIN [T0] [d_in] DigitalInverter_fa18a92b_A2D
    AINV d_in d_out DigitalInverter_fa18a92b_CORE
    AOUT [d_out] [T1] DigitalInverter_fa18a92b_D2A
.ends DigitalInverter_fa18a92b
* 2-input NAND gate with analog logic bridges and propagation delay
.subckt NAND2 A B OUT VHIGH=5 VTH=2.5 RiseDelay=1n FallDelay=1n
    .model NAND2_A2D adc_bridge(in_low={VTH} in_high={VTH})
    .model NAND2_D2A dac_bridge(out_low=0 out_high={VHIGH} out_undef={VHIGH/2})
    .model NAND2_CORE d_nand(rise_delay={RiseDelay} fall_delay={FallDelay})
    AA_IN [A] [d_a] NAND2_A2D
    AB_IN [B] [d_b] NAND2_A2D
    ANAND [d_a d_b] d_out NAND2_CORE
    AOUT [d_out] [OUT] NAND2_D2A
.ends NAND2
.model AMODEL_S adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_R adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_DP1 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP2 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP3 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP4 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP5 adc_bridge(in_low=0.8 in_high=2)

**************************************************
* Simulation settings
**************************************************
.options rshunt=1e12
.op
.end