8_2_3_Dual_Slope_ADC

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
C_C1 N5 N6 0.1u IC=0
X_DG1 N10 DigitalClock_4e731c5d Frequency=1k Duty=50 Delay=0
X_Nx N15 N14 N13 N12 CS_HEX7SEG_DISPLAY InputThreshold=2.5 HighVoltage=5
R_R1 N17 N5 100k
X_S1 N17 N18 N16 N19 0 CS_VC_SPDT_BOTTOM_CONTROL Von=2 Voff=0 Ron=1m Roff=10G
X_U1 0 N5 N6 Param3TVIRTUAL_5a7fc2f7 IOS=0 AVOL=200k BW=100meg VOS=0 IBS=0 RI=10meg VOMP=15 VOMN=-15 RO=10
X_U2 0 N6 N11 COMPARATORIDEAL_47e90bed OutputLevel=5 RiseFallTime=10n
X_U3 N9 N12 N7 N7 N15 N14 N13 N12 Param74LS93_27f4d1b7
X_U4 N11 N10 N9 DigitalAND2_5fae4f37 RiseDelay=1e-9 FallDelay=1e-9
X_U6 N19 N8 N7 DigitalAND2_5fae4f37 RiseDelay=1e-9 FallDelay=1e-9
X_U7 N12 N13 N14 N15 N8 DigitalAND4_2dafc83a RiseDelay=1n FallDelay=1n
aU8 N21 N7 NC_3 NC_2 NC_1 N19 DigitalTFlipFlop_1deeea75
X_U9 N21 CONST1 VHIGH=5
V_Ue N18 0 dc 3 ac 0 0 distof1 0 0 distof2 0 0
V_Uref N16 0 DC -5 AC 0 0 distof1 0 0 distof2 0 0
E_Uk Uk 0 N11 0 1
E_U0 U0 0 N6 0 1
E_Ui Ui 0 N17 0 1
APROBE_DP1 [N12] [d_DP1] AMODEL_DP1
APROBE_DP2 [N13] [d_DP2] AMODEL_DP2
APROBE_DP3 [N14] [d_DP3] AMODEL_DP3
APROBE_DP4 [N15] [d_DP4] AMODEL_DP4
APROBE_DP5 [N8] [d_DP5] AMODEL_DP5
APROBE_DP6 [N10] [d_DP6] AMODEL_DP6
APROBE_DP7 [N7] [d_DP7] AMODEL_DP7
APROBE_DP8 [N19] [d_DP8] AMODEL_DP8

**************************************************
* Models and supporting definitions follow
**************************************************
.subckt DigitalClock_4e731c5d OUT PARAMS: Frequency=1000 Duty=50 Delay=0
    .param period={1/Frequency}
    .param pulseWidth={Duty*0.01/Frequency}
    VCLK OUT 0 PULSE(0 5 {Delay} 1n 1n {pulseWidth} {period})
.ENDS DigitalClock_4e731c5d
.func CS_HEX7SEG_CODE(va,vb,vc,vd,vth) (((va>vth)?1:0)+2*((vb>vth)?1:0)+4*((vc>vth)?1:0)+8*((vd>vth)?1:0))
.func CS_HEX7SEG_MATCH(code,target) ((abs(code-target)<0.5)?1:0)
.subckt CS_HEX7SEG_DISPLAY IND INC INB INA PARAMS: InputThreshold=2.5 HighVoltage=5
    BSEG_A seg_a 0 V = HighVoltage*(CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),0)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),2)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),3)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),5)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),6)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),7)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),8)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),9)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),10)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),12)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),14)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),15))
    BSEG_B seg_b 0 V = HighVoltage*(CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),0)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),1)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),2)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),3)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),4)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),7)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),8)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),9)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),10)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),13))
    BSEG_C seg_c 0 V = HighVoltage*(CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),0)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),1)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),3)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),4)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),5)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),6)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),7)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),8)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),9)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),10)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),11)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),13))
    BSEG_D seg_d 0 V = HighVoltage*(CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),0)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),2)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),3)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),5)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),6)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),8)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),9)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),11)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),12)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),13)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),14))
    BSEG_E seg_e 0 V = HighVoltage*(CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),0)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),2)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),6)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),8)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),10)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),11)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),12)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),13)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),14)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),15))
    BSEG_F seg_f 0 V = HighVoltage*(CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),0)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),4)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),5)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),6)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),8)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),9)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),10)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),11)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),12)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),14)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),15))
    BSEG_G seg_g 0 V = HighVoltage*(CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),2)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),3)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),4)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),5)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),6)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),8)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),9)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),10)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),11)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),13)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),14)+CS_HEX7SEG_MATCH(CS_HEX7SEG_CODE(V(INA),V(INB),V(INC),V(IND),InputThreshold),15))
.ends CS_HEX7SEG_DISPLAY
.model Resistor_1d9c8cf9a r(tc1=0 tc2=0 tnom=27)
.SUBCKT CS_VC_SPDT_BOTTOM_CONTROL inA outA1 outA2 ctrlp ctrln PARAMS: Ron=1m Roff=10G Von=2 Voff=0
    E_CONTROL_NORMALIZED control_normalized ctrln VALUE={(V(ctrlp,ctrln)-Voff)/(Von-Voff)}
    E_CONTROL_INVERTED control_inverted ctrln VALUE={1-(V(ctrlp,ctrln)-Voff)/(Von-Voff)}
    S1 inA outA1 control_normalized ctrln CS_VC_SPDT_BOTTOM_CONTROL_NO
    S2 inA outA2 control_inverted ctrln CS_VC_SPDT_BOTTOM_CONTROL_NC
    .MODEL CS_VC_SPDT_BOTTOM_CONTROL_NO SW(Ron={Ron} Roff={Roff} Vt=0.5 Vh=0.499)
    .MODEL CS_VC_SPDT_BOTTOM_CONTROL_NC SW(Ron={Ron} Roff={Roff} Vt=0.5 Vh=0.499)
    R_STAB_COM inA ctrln 1T
    R_STAB_NO outA1 ctrln 1T
    R_STAB_NC outA2 ctrln 1T
.ENDS CS_VC_SPDT_BOTTOM_CONTROL
.model Param3TVIRTUAL_5a7fc2f7_D1 d(n=0.1)
.subckt Param3TVIRTUAL_5a7fc2f7 in_pos in_neg out params: VOS=0 IBS=0 IOS=0 AVOL=200K BW=100M RI=10M RO=10 VOMP=12 VOMN=-12

    * Input Stage: Rin, Ibias, Voffset
    VOS in_pos 4 {VOS}
    Ibias1 4 0 {IBS}
    Ibias2 in_neg 0 {IBS}
    IOS 4 in_neg {IOS/2}
    Rin 4 in_neg {RI}

    *Middle stage: Gain, frequency, voltage limiting
    Bgain 0 6 I={v(4,in_neg)*AVOL/1meg}
    R1 6 0 1meg
    CP1 6 0 {AVOL/(2*3.141592653589793*1meg*BW)}


    Vpos 9 0 {VOMP}
    Dlimit_pos 6 9 Param3TVIRTUAL_5a7fc2f7_D1

    Vneg 10 0 {VOMN}
    Dlimit_neg 10 6 Param3TVIRTUAL_5a7fc2f7_D1


    *Output stage: Buffer, output resistance
    E2 7 0 6 0 1
    Rout 7 out {RO}
.ends
.subckt COMPARATORIDEAL_47e90bed in+ in- out params: OutputLevel=5 RiseFallTime=10n
    B_out_TARGET out_target 0 V={V(in+)>V(in-) ? OutputLevel : 0}
    R_out_EDGE out_target out_edge 1
    C_out_EDGE out_edge 0 {RiseFallTime/2.197224577+1f}
    B_out_BUFFER out 0 V={min(max(V(out_edge),0),OutputLevel)}
.ends COMPARATORIDEAL_47e90bed
.model Param74LS93_27f4d1b7_Jkff d_jkff (clk_delay=1e-9 set_delay=1e-9 reset_delay=1e-9 ic=0 rise_delay=1e-9 fall_delay=1e-9)
.model Param74LS93_27f4d1b7_Inv d_inverter (rise_delay=10p fall_delay=10p)
.model Param74LS93_27f4d1b7_Low d_pulldown
.model Param74LS93_27f4d1b7_High d_pullup
.model Param74LS93_27f4d1b7_And d_and
**********************
*74LS93 COUNTER BINARY 4-BIT, ASYNCHRONOUS
***
.subckt Param74LS93_27f4d1b7 clka clkb r02 r01 qd qc qb qa
    *FAMILY TTLin TTLin TTLin TTLin TTLout
    *pinout N 14 1 3 2 11 8 9 12 5:VCC=5 GND=10
    *pinout J 11 14 1 3 2 11 8 9 12 5:VCC=5 GND=10
    *pinout D 11 14 1 3 2 11 8 9 12 5:VCC=5 GND=10

    aand [r01 r02] rst Param74LS93_27f4d1b7_And
    ainv1 clka nclka Param74LS93_27f4d1b7_Inv
    ainv2 clkb nclkb Param74LS93_27f4d1b7_Inv

    ah hi Param74LS93_27f4d1b7_High
    al lo Param74LS93_27f4d1b7_Low

    ajkffaqa hi hi nclka lo rst qa nqa Param74LS93_27f4d1b7_Jkff
    ajkffbqb hi hi nclkb lo rst qb nqb Param74LS93_27f4d1b7_Jkff
    ajkffbqc hi hi nqb lo rst qc nqc Param74LS93_27f4d1b7_Jkff
    ajkffbqd hi hi nqc lo rst qd nqd Param74LS93_27f4d1b7_Jkff




.ends
* 2-input AND gate with analog logic bridges and propagation delay
.subckt DigitalAND2_5fae4f37 T0 T1 T2 RiseDelay=1e-9 FallDelay=1e-9
    .model DigitalAND2_5fae4f37_A2D adc_bridge(in_low=2.5 in_high=2.5)
    .model DigitalAND2_5fae4f37_D2A dac_bridge(out_low=0 out_high=5 out_undef=2.5)
    .model DigitalAND2_5fae4f37_CORE d_and(rise_delay={RiseDelay} fall_delay={FallDelay})
    AA_IN [T0] [d_t0] DigitalAND2_5fae4f37_A2D
    AT1_IN [T1] [d_t1] DigitalAND2_5fae4f37_A2D
    AAND [d_t0 d_t1] d_out DigitalAND2_5fae4f37_CORE
    AOUT [d_out] [T2] DigitalAND2_5fae4f37_D2A
.ends DigitalAND2_5fae4f37
.model DigitalAND4_2dafc83a_DigitalAND42dafc83aA2D adc_bridge(in_low=2.5 in_high=2.5)
.model DigitalAND4_2dafc83a_DigitalAND42dafc83aD2A dac_bridge(out_low=0 out_high=5 out_undef=2.5)
* 4-input AND gate with analog logic bridges and propagation delay
.subckt DigitalAND4_2dafc83a T0 T1 T2 T3 T4 params: RiseDelay=1e-9 FallDelay=1e-9
    .model DigitalAND4_2dafc83a_DigitalAND42dafc83aCORE d_and(rise_delay={RiseDelay} fall_delay={FallDelay})
    AT0_IN [T0] [d_t0] DigitalAND4_2dafc83a_DigitalAND42dafc83aA2D
    AT1_IN [T1] [d_t1] DigitalAND4_2dafc83a_DigitalAND42dafc83aA2D
    AT2_IN [T2] [d_t2] DigitalAND4_2dafc83a_DigitalAND42dafc83aA2D
    AT3_IN [T3] [d_t3] DigitalAND4_2dafc83a_DigitalAND42dafc83aA2D
    AAND [d_t0 d_t1 d_t2 d_t3] d_out DigitalAND4_2dafc83a_DigitalAND42dafc83aCORE
    AOUT [d_out] [T4] DigitalAND4_2dafc83a_DigitalAND42dafc83aD2A
.ends DigitalAND4_2dafc83a
.model DigitalTFlipFlop_1deeea75 d_tff (rise_delay=1n fall_delay=1n clk_delay=1e-9 set_delay=1e-9 reset_delay=1e-9 ic=0)
* Constant logic-high source
.subckt CONST1 OUT VHIGH=5
    BOUT OUT 0 V = { VHIGH }
.ends CONST1
.model AMODEL_DP1 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP2 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP3 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP4 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP5 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP6 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP7 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP8 adc_bridge(in_low=0.8 in_high=2)

**************************************************
* Simulation settings
**************************************************
.options rshunt=1e12
.options noopalter
.tran 20u 1e12 0 20u uic
.save V(U0) V(Ui) V(Uk) v(x_Nx.seg_a) v(x_Nx.seg_b) v(x_Nx.seg_c) v(x_Nx.seg_d) v(x_Nx.seg_e) v(x_Nx.seg_f) v(x_Nx.seg_g) v(N19,0)
.end