example 2

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
V_Digital Constant N1 0 DC 5
X_NOT N2 N3 INV VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
X_S1 N1 0 N2 TDSW1_1bcd2ff9 OnTime=0.5 OffTime=1
APROBE_DP1 [N2] [d_DP1] AMODEL_DP1
APROBE_DP2 [N3] [d_DP2] AMODEL_DP2

**************************************************
* Models and supporting definitions follow
**************************************************
* Generic digital inverter (NOT gate) with normalized propagation delay
.subckt INV IN OUT VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
    BTARGET TARGET 0 V = {(V(IN) > VTH) ? 0 : VHIGH}
    GDELAY STATE 0 VALUE = {(V(TARGET) > V(STATE)) ? (V(STATE)-V(TARGET))/(((RiseDelay > 1e-15) ? RiseDelay : 1e-15)/(0.69314718056*1e-9)) : (V(STATE)-V(TARGET))/(((FallDelay > 1e-15) ? FallDelay : 1e-15)/(0.69314718056*1e-9))}
    CDELAY STATE 0 1n
    BOUT OUT 0 V = {(V(STATE) >= VHIGH/2) ? VHIGH : 0}
.ends INV
.SUBCKT TDSW1_1bcd2ff9 ON OFF COMMON PARAMS: OnTime=0.5 OffTime=1
    BSTATE STATE 0 V={((OnTime < OffTime) ? ((time > OnTime) ? ((time > OffTime) ? 0 : 1) : 0) : ((time > OffTime) ? ((time > OnTime) ? 1 : 0) : 1))}
    BSTATE_INV STATE_INV 0 V={1-V(STATE)}
    S_ON ON COMMON STATE 0 TDSW1_1bcd2ff9_SW
    S_OFF OFF COMMON STATE_INV 0 TDSW1_1bcd2ff9_SW
    .MODEL TDSW1_1bcd2ff9_SW SW(Ron=10m Roff=1Meg Vt=0.25 Vh=0.2495)
.ENDS TDSW1_1bcd2ff9
.model AMODEL_DP1 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP2 adc_bridge(in_low=0.8 in_high=2)

**************************************************
* Simulation settings
**************************************************
.options rshunt=1e12
.tran 20u 1e12 0 20u
.save v(x_S1.state)
.end