6_1_1_Einfaches_RS_Flipflop (Sam)

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
V_Reset N4 0 DC 0
V_Set N3 0 DC 0
X_U10 N3 N4 N6 N7 RS_LATCH
X_U11 N4 N1 DigitalInverter_fa18a92b RiseDelay=1n FallDelay=1n
X_U12 N3 N8 DigitalInverter_fa18a92b RiseDelay=1n FallDelay=1n
X_U13 N4 N9 DigitalInverter_fa18a92b RiseDelay=1n FallDelay=1n
X_U14 N3 N2 N5 OR2 VHIGH=5 VTH=2.5
X_U15 N1 N5 N2 AND2 VHIGH=5 VTH=2.5
X_U16 N8 N11 N10 NAND2 VHIGH=5 VTH=2.5
X_U17 N10 N9 N11 NAND2 VHIGH=5 VTH=2.5
APROBE_S [N3] [d_S] AMODEL_S
APROBE_R [N4] [d_R] AMODEL_R
APROBE_DP1 [N5] [d_DP1] AMODEL_DP1
APROBE_DP2 [N10] [d_DP2] AMODEL_DP2
APROBE_DP3 [N11] [d_DP3] AMODEL_DP3
APROBE_DP4 [N6] [d_DP4] AMODEL_DP4
APROBE_DP5 [N7] [d_DP5] AMODEL_DP5

**************************************************
* Models and supporting definitions follow
**************************************************
* ---------------------------------------------------------
* Setzdominantes RS-Flipflop (NOR-Latch)
* Pins: S  R  Q  Qbar
* ---------------------------------------------------------
.subckt RS_LATCH S R Q Q_N

    X1 Q     S     Q_N  NOR2
    X2 Qbar  R     Q    NOR2

.ends RS_LATCH

.subckt NOR2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = {(V(A) > VTH || V(B) > VTH) ? 0 : VHIGH}
.ends NOR2
.model DigitalInverter_fa18a92b_DigitalInverterFa18a92bA2D adc_bridge(in_low=2.5 in_high=2.5)
.model DigitalInverter_fa18a92b_DigitalInverterFa18a92bD2A dac_bridge(out_low=0 out_high=5 out_undef=2.5)
* 1-input INVERTER gate with analog logic bridges and propagation delay
.subckt DigitalInverter_fa18a92b T0 T1 params: RiseDelay=1e-9 FallDelay=1e-9
    .model DigitalInverter_fa18a92b_DigitalInverterFa18a92bCORE d_inverter(rise_delay={RiseDelay} fall_delay={FallDelay})
    AT0_IN [T0] [d_t0] DigitalInverter_fa18a92b_DigitalInverterFa18a92bA2D
    AINVERTER d_t0 d_out DigitalInverter_fa18a92b_DigitalInverterFa18a92bCORE
    AOUT [d_out] [T1] DigitalInverter_fa18a92b_DigitalInverterFa18a92bD2A
.ends DigitalInverter_fa18a92b
* OR 2-Input gate, ideal behavioral
.subckt OR2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = {(V(A) > VTH) || (V(B) > VTH) ? VHIGH : 0}
.ends OR2
* AND 2-Input gate, ideal behavioral
.subckt AND2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = {((V(A) > VTH) && (V(B) > VTH)) ? VHIGH : 0}
.ends AND2
* NAND 2-Input gate, ideal behavioral
.subckt NAND2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = {(V(A) > VTH) && (V(B) > VTH) ? 0 : VHIGH}
.ends NAND2
.model AMODEL_S adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_R adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_DP1 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP2 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP3 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP4 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP5 adc_bridge(in_low=0.8 in_high=2)

**************************************************
* Simulation settings
**************************************************
.options rshunt=1e12
.op
.save V(N3) V(N4) V(N5) V(N10) V(N11) V(N6) V(N7)
.end