240V Split Phase (Center Ground) Idle - Correct

MI

mik3pass

·

Created Jul 16, 2026

·

Updated Jul 16, 2026

Schematic preview for 240V Split Phase (Center Ground) Idle - Correct
Details

Components

4


Schematic

Yes


Simulation

Transient analysis


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1

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Components used

Components used
4 components
NameManufacturerMPNCountType

Capacitor

Generic

15

Official

Resistor

Generic

6

Official

1N4007 Rectifier Diode

Diodes, Inc.

1N4007

3

Official

AC Voltage Source

Generic

2

Official

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
C_C10 N12 N24 20n IC=0
C_C11 N24 N8 20n IC=0
C_C12 N2 N10 1n IC=0
C_C13 N14 N21 20n IC=0
C_C14 N21 N10 20n IC=0
C_C15 N1 N9 1n IC=0
C_C16 N7 N22 20n IC=0
C_C17 N22 N9 20n IC=0
C_C3 N15 N6 1n IC=0
C_C4 N12 N8 5u5 IC=0
C_C5 N13 N2 1n IC=0
C_C6 N14 N10 5u5 IC=0
C_C7 N11 N1 1n IC=0
C_C8 N7 N9 5u5 IC=0
C_C9 N6 N8 1n IC=0
D_D1 N17 N15 DI_1N4007
D_D2 N18 N13 DI_1N4007
D_D3 N16 N11 DI_1N4007
R_R1 N15 N8 540K
R_R2 N12 N17 56
R_R3 N13 N10 540K
R_R4 N14 N18 56
R_R5 N11 N9 540K
R_R6 N7 N16 56
vV1 N15 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 120 60 0 0 0 )
vV2 0 N8 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 120 60 0 0 0 )
vV3 N13 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 120 60 0 0 0 )
vV4 0 N10 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 120 60 0 0 0 )
vV5 N11 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 120 60 0 0 180 )
vV6 0 N9 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 120 60 0 0 180 )
E_VP1 VP1 0 N12 0 1
V_IP2 N6 0 0
V_IP4 N2 0 0
V_IP6 N1 0 0
V_IP3 N24 0 0
V_IP5 N21 0 0
V_IP7 N22 0 0

**************************************************
* Models and supporting definitions follow
**************************************************
.MODEL DI_1N4007 D (IS=76.9p RS=42.0m BV=1.00k IBV=5.00u CJO=26.5p M=0.333 N=1.45 TT=4.32u)

**************************************************
* Simulation settings
**************************************************
.tran 333u 0.3 0 333u
.save V(VP1) I(V_IP2) I(V_IP3) I(V_IP4) I(V_IP5) I(V_IP6) I(V_IP7)
.end

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