Project_1_abhi

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
X_U1 N2 N1 N3 AND2 VHIGH=5 VTH=2.5
X_U2 N1 N2 N4 XOR2 VHIGH=5 VTH=2.5
V_U3 N2 0 DC 5
V_U4 N1 0 DC 5
APROBE_DP1 [N4] [d_DP1] AMODEL_DP1
APROBE_DP2 [N3] [d_DP2] AMODEL_DP2

**************************************************
* Models and supporting definitions follow
**************************************************
* AND 2-Input gate, ideal behavioral
.subckt AND2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = {((V(A) > VTH) && (V(B) > VTH)) ? VHIGH : 0}
.ends AND2
* XOR 2-Input gate, ideal behavioral
.subckt XOR2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = {((V(A) > VTH) != (V(B) > VTH)) ? VHIGH : 0}
.ends XOR2
.model AMODEL_DP1 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP2 adc_bridge(in_low=0.8 in_high=2)

**************************************************
* Simulation settings
**************************************************
.tran 20u 100m 0 20u
.save time V(N4) V(N3)
.end