Trying 7400

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
X_7400_IC1 {1A} {1B} {1Y} {2A} {2B} {2Y} 0 {3Y} {3A} {3B} {4Y} {4A} {4B} N2 NAND2x4
V_V1 N2 0 dc 5 ac 0 0 distof1 0 0 distof2 0 0
E_VP1 VP1 0 N3 0 1
E_VP2 VP2 0 N4 0 1
E_VP3 VP3 0 N5 0 1
E_VP4 VP4 0 N6 0 1

**************************************************
* Models and supporting definitions follow
**************************************************
***********************
* Quad 2-Input NAND gate (behavioral model)
* Pin order follows the classic 7400:
*   1A 1B 1Y  2A 2B 2Y  GND  3Y 3A 3B  4Y 4A 4B  VCC
***********************
.subckt NAND2x4 1A 1B 1Y  2A 2B 2Y  GND  3Y 3A 3B  4Y 4A 4B  VCC
    + VHIGH=5 VTH=2.5

    * Gate 1
    B1 1Y GND V = {(V(1A) > VTH) && (V(1B) > VTH) ? 0 : VHIGH}

    * Gate 2
    B2 2Y GND V = {(V(2A) > VTH) && (V(2B) > VTH) ? 0 : VHIGH}

    * Gate 3
    B3 3Y GND V = {(V(3A) > VTH) && (V(3B) > VTH) ? 0 : VHIGH}

    * Gate 4
    B4 4Y GND V = {(V(4A) > VTH) && (V(4B) > VTH) ? 0 : VHIGH}

.ends NAND2x4

**************************************************
* Simulation settings
**************************************************
.tran 100u 100m 0
.save V(VP1) V(VP2) V(VP3) V(VP4)
.end