NAND

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
X_A N3 0 TOGGLEABLE_DIGITAL_CONSTANT state=0 logicLow=0 logicHigh=5
X_B N2 0 TOGGLEABLE_DIGITAL_CONSTANT state=0 logicLow=0 logicHigh=5
R_RLOAD N4 0 10K
X_U1 N3 N2 N4 NAND2 VHIGH=5 VTH=2.5
APROBE_DP1 [N3] [d_DP1] AMODEL_DP1
APROBE_DP2 [N2] [d_DP2] AMODEL_DP2
APROBE_DP4 [N4] [d_DP4] AMODEL_DP4

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* Models and supporting definitions follow
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* Toggleable digital constant logic-level source
.subckt TOGGLEABLE_DIGITAL_CONSTANT OUT GND PARAMS: state=0 logicLow=0 logicHigh=5
    BOUT OUT GND V = {logicLow+(logicHigh-logicLow)*state}
.ends TOGGLEABLE_DIGITAL_CONSTANT
* NAND 2-Input gate, ideal behavioral
.subckt NAND2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = {(V(A) > VTH) && (V(B) > VTH) ? 0 : VHIGH}
.ends NAND2
.model AMODEL_DP1 adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_DP2 adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_DP4 adc_bridge(in_low=3.3 in_high=3.3)

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* Simulation settings
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.op
.save V(N3) V(N2) V(N4)
.end