XOR
fran23
·
Created Sep 18, 2026
·
Updated Sep 18, 2026
Details
Components
1
Schematic
Yes
Simulation
Interactive operating point
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1
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About this circuit
A logic threshold demo sweeping one input while the other two inputs stay high, showing the NAND output transition.
Circuit notes
3-Input NAND Gate Logic Threshold Sweep
Application
This circuit shows a 3-input NAND gate used as a simple logic-condition detector: the output goes low only when all three inputs are high.
Schematic Organization
Inputs A, B, and C enter from the left. B and C are fixed at 5 V, while A is intended to be swept from 0 V to 5 V. The output drives a 10K load on the right for a direct logic-level check.
Expected Behavior
With VTH set to 2.5 V and VHIGH set to 5 V, Vout remains near 5 V while A is below the threshold. Once A is above 2.5 V and B and C are already high, Vout falls near 0 V.
Suggested Experiments
- Change VTH from 2.5 V to 1.5 V and rerun the sweep.
- Set B or C to 0 V and confirm that Vout remains high across the A sweep.
- Change VHIGH from 5 V to 3.3 V for a lower-voltage logic example.
Featured Component
The 3-input NAND Gate is the featured behavioral equivalent of the Micro-Cap NAND primitive. It keeps the same A, B, C, and OUT external pins while using a supported ngspice expression.
Components used
Components used
1 component
SPICE netlist
* **************************************************
* Generated from CircuitSim Schematic
**************************************************
X_A N4 0 TOGGLEABLE_DIGITAL_CONSTANT state=1 logicLow=0 logicHigh=5
X_B N3 0 TOGGLEABLE_DIGITAL_CONSTANT state=1 logicLow=0 logicHigh=5
R_RLOAD N1 0 10K
X_U1 N4 N3 N1 XOR2 VHIGH=5 VTH=2.5
APROBE_DP1 [N4] [d_DP1] AMODEL_DP1
APROBE_DP2 [N3] [d_DP2] AMODEL_DP2
APROBE_DP4 [N1] [d_DP4] AMODEL_DP4
**************************************************
* Models and supporting definitions follow
**************************************************
* Toggleable digital constant logic-level source
.subckt TOGGLEABLE_DIGITAL_CONSTANT OUT GND PARAMS: state=0 logicLow=0 logicHigh=5
BOUT OUT GND V = {logicLow+(logicHigh-logicLow)*state}
.ends TOGGLEABLE_DIGITAL_CONSTANT
* XOR 2-Input gate, ideal behavioral
.subckt XOR2 A B OUT VHIGH=5 VTH=2.5
BOUT OUT 0 V = {((V(A) > VTH) != (V(B) > VTH)) ? VHIGH : 0}
.ends XOR2
.model AMODEL_DP1 adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_DP2 adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_DP4 adc_bridge(in_low=3.3 in_high=3.3)
**************************************************
* Simulation settings
**************************************************
.op
.save V(N4) V(N3) V(N1)
.endTry this circuit yourself
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