AD22050N Difference Amplifier AD22050/AD22057 Offset Difference Amplifier (Copy)

MA

Mariam abdulrahman

·

Created Sep 20, 2026

·

Updated Sep 20, 2026

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Details

Components

2


Schematic

Yes


Simulation

Transient analysis


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About this circuit

A cascaded difference-amplifier path uses the offset input to define the output baseline.

Components used

Components used
2 components
NameManufacturerMPNCountType

AD22050N Difference Amplifier

Analog Devices

AD22050N

1

Official

Dual Rail Power Supply

Generic

1

Official

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
* net label +15V joins +15V::component:node-6969b19b-8e9a-4d26-93eb-e224b4c5185d:VPLUS NET_002::component:u1:99
* net label -15V joins -15V::component:node-6969b19b-8e9a-4d26-93eb-e224b4c5185d:VMINUS NET_001::component:u1:50
V_PS1P N7 0 DC 15
V_PS1N 0 0 DC -15
R_RLOAD N4 0 10K
X_U1 N2 N3 N7 0 N5 N5 0 N4 AD22050N_AD
V_VINN N3 0 DC 1.00
V_VINP N2 0 DC 1.10
E_VP_INP VP_INP 0 N2 0 1
E_VP_INN VP_INN 0 N3 0 1
E_VP_OUT VP_OUT 0 N4 0 1

**************************************************
* Models and supporting definitions follow
**************************************************
* Split from analog.lib lines 67362-67504
* Model: AD22050N_AD
* AD22050N SPICE Macro-model            Rev. A, 9/95
*                                       ARG / ADSC
*
* This version of the AD22050 model simulates the worst-case
* parameters of the 'N' grade. The worst-case parameters
* used correspond to those in the data sheet.
*
* Copyright 1995 by Analog Devices
*
* Refer to "README.DOC" file for License Statement. Use of
* this model indicates your acceptance of the terms and pro-
* visions in the License Statement.
*
* Node assignments
*                non-inverting input
*                |  inverting input
*                |  |  positive supply
*                |  |  |  negative supply
*                |  |  |  |  A1 out
*                |  |  |  |  |  A2 in
*                |  |  |  |  |  |  offset
*                |  |  |  |  |  |  |  output
*                |  |  |  |  |  |  |  |
.SUBCKT AD22050N_AD 1  2  99 50 30 31 40 49
    *
    * A1 INPUT ATTENUATORS, GAIN, AND OFFSET RESISTORS
    *
    R1 1 3 200K
    R2 2 4 200K
    RS1 3 16 1K
    RS2 4 18 1K
    R3 3 5 41K
    R4 4 6 41K
    R5 5 6 2.566K TC=-134U
    R6 5 50 250
    R7 6 50 250
    R8 5 19 9K
    R9 6 7 10K
    R10 19 40 2K
    R11 19 50 2K
    R12 7 30 100K
    R16 7 50 10K
    C1 16 50 5P
    C2 17 50 5P
    *
    * A1 INPUT STAGE AND POLE AT 1MHZ
    *
    I1 99 8 7.55U
    Q1 11 16 9 QP 1
    Q2 12 17 10 QP 1
    R21 11 50 6.89671K
    R22 12 50 6.89671K
    R23 8 9 .335
    R24 8 10 .335
    C3 11 12 11.5P
    EOS 61 17 POLY(1) 33 0 -225.534U 1.698
    ETC 18 61 POLY(1) 60 0 -49.665M 1
    ITC 0 60 49.665U
    RTC 60 0 1E3 TC=-102U
    *
    * GAIN STAGE AND DOMINANT POLE AT 400HZ
    *
    EREF 98 50 POLY(2) 99 0 50 0 0 0.5 0.5
    G1 98 13 12 11 144.997U
    R25 13 98 6.89671E6
    C4 13 98 57.6923P
    D1 13 99 DX
    D2 50 13 DX
    *
    * COMMON MODE STAGE WITH ZERO AT 1KHZ
    *
    ECM 32 0 POLY(2) 1 0 2 0 0 0.5 0.5
    R28 32 33 1E6
    R29 33 0 10
    CCM 32 33 159P
    *
    * NEGATIVE ZERO AT 0.6MHZ
    *
    E1 23 98 13 98 1E6
    R26 23 24 1E3
    R27 24 98 1E-3
    FNZ 23 24 VNZ -1
    ENZ 25 98 23 24 1
    VNZ 26 98 DC 0
    CNZ 25 26 265P
    *
    * POLE AT 5MHZ
    *
    G2 98 20 24 98 1E-6
    R30 20 98 1E6
    C5 20 98 32F
    *
    * A1 OUTPUT STAGE
    *
    EIN1 99 27 POLY(1) 20 98 1.5072 1.124
    Q216 50 27 28 QP375 3.444
    Q218 7 29 99 QP350 9.913
    R31 28 29 27K
    I2 99 29 4.75U
    *
    * A2 INPUT STAGE
    *
    I3 99 34 2.516667U
    Q3 35 31 37 QP 1
    Q4 36 39 38 QP 1
    R32 35 50 106.103K
    R33 36 50 106.103K
    R34 34 37 85.414K
    R35 34 38 85.414K
    R13 40 41 20K
    R14 41 50 20K
    R15 41 49 10K
    R17 39 41 95K
    *
    * A2 1ST GAIN STAGE AND SLEW RATE
    *
    G3 98 42 36 35 30.159U
    R36 42 98 1E6
    E2 99 43 POLY(1) 99 98 -0.473 1
    E3 44 50 POLY(1) 98 50 -0.473 1
    D3 42 43 DX
    D4 44 42 DX
    *
    * A2 2ND GAIN STAGE AND DOMINANT POLE AT 12HZ
    *
    G4 98 45 42 98 2.5U
    R37 45 98 132.629E6
    C7 45 98 100P
    D5 45 59 DX
    D6 55 45 DX
    VC1 59 99 5
    VC2 50 55 5
    *
    * NEGATIVE ZERO AT 1MHZ
    *
    E4 51 98 45 98 1E6
    R38 51 52 1E6
    R39 52 98 1
    FNZ2 51 52 VNZ2 -1
    ENZ2 53 98 51 52 1
    VNZ2 54 98 0
    CNZ2 53 54 159F
    *
    * A2 OUTPUT STAGE
    *
    ISY 99 50 469U
    EIN2 99 56 POLY(1) 52 98 1.6901 112.132E-3
    RIN 46 56 10K
    Q316 50 46 47 QP375 1.778
    Q310 50 47 48 QP375 5.925
    Q318 49 48 57 50 QP350 9.913
    I4 99 47 4.75U
    I5 99 48 9.5U
    VSC 99 57 0
    FSC 58 99 VSC 1
    QSC 46 58 99 QP350 1
    RSC 99 58 89
    *
    * MODELS USED
    *
    .MODEL QP350 PNP(IS=1.4E-15 BF=70 CJE=.012P CJC=.06P RE=20 RB=350
    +RC=200)
    .MODEL QP375 PNP(IS=1.4E-15 CJE=.01P CJC=.05P RE=20 RC=400 RB=100)
    .MODEL QP PNP(IS=1.4E-15 BF=150 CJE=.012P CJC=.06P RE=20 RB=350 VA=100)
    .MODEL DX D(CJO=1F RS=.1)
.ENDS

**************************************************
* Simulation settings
**************************************************
.tran .000001 .001 0
.save V(VP_INP) V(VP_INN) V(VP_OUT)
.end

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