6_1_3_Taktzustandsgesteuertes_D_Flipflop

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
X_Clk N11 DigitalClock_4e731c5d Frequency=10 Duty=50 Delay=0
V_Data N6 0 DC 0
X_U1 N6 N5 INV VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
aU1 N6 N5 N11 N1 N2 N3 N4 DigitalSRLatch_ad775ab8
V_U10 N2 0 DC 0
X_U2 N9 N7 INV VHIGH=5 VTH=2.5 RiseDelay=5n FallDelay=5n
X_U3 N7 N8 INV VHIGH=5 VTH=2.5 RiseDelay=5n FallDelay=5n
X_U4 N8 N10 INV VHIGH=5 VTH=2.5 RiseDelay=5n FallDelay=5n
X_U7 N10 N9 NC_1 AND2 VHIGH=5 VTH=2.5
V_U9 N1 0 DC 0
APROBE_Data [N6] [d_Data] AMODEL_Data
APROBE_DP1 [N3] [d_DP1] AMODEL_DP1
APROBE_DP2 [N4] [d_DP2] AMODEL_DP2
APROBE_DP3 [N11] [d_DP3] AMODEL_DP3
APROBE_DP4 [N9] [d_DP4] AMODEL_DP4

**************************************************
* Models and supporting definitions follow
**************************************************
.subckt DigitalClock_4e731c5d OUT PARAMS: Frequency=1000 Duty=50 Delay=0
    .param period={1/Frequency}
    .param pulseWidth={Duty*0.01/Frequency}
    VCLK OUT 0 PULSE(0 5 {Delay} 1n 1n {pulseWidth} {period})
.ENDS DigitalClock_4e731c5d
* Generic digital inverter (NOT gate) with normalized propagation delay
.subckt INV IN OUT VHIGH=5 VTH=2.5 RiseDelay=1e-9 FallDelay=1e-9
    BTARGET TARGET 0 V = {(V(IN) > VTH) ? 0 : VHIGH}
    GDELAY STATE 0 VALUE = {(V(TARGET) > V(STATE)) ? (V(STATE)-V(TARGET))/(((RiseDelay > 1e-15) ? RiseDelay : 1e-15)/(0.69314718056*1e-9)) : (V(STATE)-V(TARGET))/(((FallDelay > 1e-15) ? FallDelay : 1e-15)/(0.69314718056*1e-9))}
    CDELAY STATE 0 1n
    BOUT OUT 0 V = {(V(STATE) >= VHIGH/2) ? VHIGH : 0}
.ends INV
.model DigitalSRLatch_ad775ab8 d_srlatch(rise_delay=1n fall_delay=1n sr_delay=1e-9 enable_delay=1e-9 set_delay=1e-9 reset_delay=1e-9 ic=0)
* AND 2-Input gate, ideal behavioral
.subckt AND2 A B OUT VHIGH=5 VTH=2.5
    BOUT OUT 0 V = {((V(A) > VTH) && (V(B) > VTH)) ? VHIGH : 0}
.ends AND2
.model AMODEL_Data adc_bridge(in_low=3.3 in_high=3.3)
.model AMODEL_DP1 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP2 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP3 adc_bridge(in_low=0.8 in_high=2)
.model AMODEL_DP4 adc_bridge(in_low=0.8 in_high=2)

**************************************************
* Simulation settings
**************************************************
.options rshunt=1e12
.tran 200u 1e12 0 200u
.save time V(N6) V(N3) V(N4) V(N11) V(N9)
.end