test

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
R_R1 N2 N1 1K
R_R2 N5 N2 1K
X_U1 0 N2 N5 Param3TVIRTUAL_5a7fc2f7 IOS=0 AVOL=200K BW=100meg VOS=0 IBS=0 RI=10meg VOMP=12 VOMN=-12 RO=10
V_V1 N1 0 dc 0 ac 1 0 distof1 0 0 distof2 0 0 sin ( 0 10m 60 0 0 0 )
E_VP1 VP1 0 N5 0 1

**************************************************
* Models and supporting definitions follow
**************************************************
.model Resistor_1d9c8cf9a r(tc1=0 tc2=0 tnom=27)
.model Param3TVIRTUAL_5a7fc2f7_D1 d(n=0.1)
.subckt Param3TVIRTUAL_5a7fc2f7 in_pos in_neg out params: VOS=0 IBS=0 IOS=0 AVOL=200K BW=100M RI=10M RO=10 VOMP=12 VOMN=-12

    * Input Stage: Rin, Ibias, Voffset
    VOS in_pos 4 {VOS}
    Ibias1 4 0 {IBS}
    Ibias2 in_neg 0 {IBS}
    IOS 4 in_neg {IOS/2}
    Rin 4 in_neg {RI}

    *Middle stage: Gain, frequency, voltage limiting
    Bgain 0 6 I={v(4,in_neg)*AVOL/1meg}
    R1 6 0 1meg
    CP1 6 0 {AVOL/(2*3.141592653589793*1meg*BW)}


    Vpos 9 0 {VOMP}
    Dlimit_pos 6 9 Param3TVIRTUAL_5a7fc2f7_D1

    Vneg 10 0 {VOMN}
    Dlimit_neg 10 6 Param3TVIRTUAL_5a7fc2f7_D1


    *Output stage: Buffer, output resistance
    E2 7 0 6 0 1
    Rout 7 out {RO}
.ends

**************************************************
* Simulation settings
**************************************************
.tran 0.000001 100m 0 200p
.save V(VP1)
.end