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New Circuit

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nukpohor

·

Created Sep 21, 2026

·

Updated Oct 2, 2026

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Components

8


Schematic

Yes


Simulation

Transient analysis


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Components used

Components used
8 components
NameManufacturerMPNCountType

Capacitor

Generic

—

2

Official

Resistor

Generic

—

2

Official

7-Segment Display Common Anode

Generic

7SEG-CA

1

Official

74LS47N

Generic

74LS47N

1

Official

DC Voltage Source

Generic

—

1

Official

Dynamic Light Bulb

—

—

1

Official

LM555CN

IPC-2221A/2222

LM555CN

1

Official

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
C_C1 N3 0 47uF IC=0
C_C2 N23 0 0.01uF IC=0
R_LAMP1 N5 0 0
XQ1 N7 N8 N9 N10 N11 N11 N11 N12 N15 N16 N17 N14 N13 N18 Param74LS47_8e4368a5 PARAMS: RiseDelay=1n FallDelay=1n
R_R1 N2 N22 6.8K Resistor_1d9c8cf9a__R_R1
R_R2 N22 N3 16K Resistor_1d9c8cf9a__R_R2
xU1 0 N3 N5 N2 N23 N3 N22 N2 LM555IIT_c4ad0dd4
xU2 N12 N13 N14 N15 N16 N17 N18 0 Param7SEGMENTCA_ef9d78c1 PARAMS: IS=1e-14 N=1 RS=0 IBV=100000000000000000 BV=1e30 CJO=0 M=0.5 VJ=1 ION=20m
xU3 0 0 0 0 N2 N5 N2 0 N7 N8 N9 N10 0 0 Param74LS193_bebceed8
V_V1 N2 N11 dc 9 ac 0 0 distof1 0 0 distof2 0 0

**************************************************
* Models and supporting definitions follow
**************************************************
* 74LS47N BCD-to-seven-segment behavioral model
.subckt Param74LS47_8e4368a5 A B C D LT RBI BIRBO OA OD OE OF OC OB OG params: RiseDelay=1e-7 FallDelay=1e-7
    B_N N 0 V={(V(A)>2.5)+2*(V(B)>2.5)+4*(V(C)>2.5)+8*(V(D)>2.5)}
    B_OA_TARGET OA_TARGET 0 V={((V(LT)<0.8)?0:((V(BIRBO)<0.8)?5:(((V(RBI)<0.8)&&(V(N)<0.5))?5:(((V(N)<0.5)||((V(N)>1.5)&&(V(N)<3.5))||((V(N)>4.5)&&(V(N)<9.5)))?0:5))))}
    R_OA OA_TARGET OA 1
    C_OA OA 0 {(RiseDelay+FallDelay)/2+1p}
    B_OB_TARGET OB_TARGET 0 V={((V(LT)<0.8)?0:((V(BIRBO)<0.8)?5:(((V(RBI)<0.8)&&(V(N)<0.5))?5:(((V(N)<4.5)||((V(N)>6.5)&&(V(N)<9.5)))?0:5))))}
    R_OB OB_TARGET OB 1
    C_OB OB 0 {(RiseDelay+FallDelay)/2+1p}
    B_OC_TARGET OC_TARGET 0 V={((V(LT)<0.8)?0:((V(BIRBO)<0.8)?5:(((V(RBI)<0.8)&&(V(N)<0.5))?5:(((V(N)<1.5)||((V(N)>2.5)&&(V(N)<9.5)))?0:5))))}
    R_OC OC_TARGET OC 1
    C_OC OC 0 {(RiseDelay+FallDelay)/2+1p}
    B_OD_TARGET OD_TARGET 0 V={((V(LT)<0.8)?0:((V(BIRBO)<0.8)?5:(((V(RBI)<0.8)&&(V(N)<0.5))?5:(((V(N)<0.5)||((V(N)>1.5)&&(V(N)<3.5))||((V(N)>4.5)&&(V(N)<6.5))||((V(N)>7.5)&&(V(N)<9.5)))?0:5))))}
    R_OD OD_TARGET OD 1
    C_OD OD 0 {(RiseDelay+FallDelay)/2+1p}
    B_OE_TARGET OE_TARGET 0 V={((V(LT)<0.8)?0:((V(BIRBO)<0.8)?5:(((V(RBI)<0.8)&&(V(N)<0.5))?5:(((V(N)<0.5)||((V(N)>1.5)&&(V(N)<2.5))||((V(N)>5.5)&&(V(N)<6.5))||((V(N)>7.5)&&(V(N)<8.5)))?0:5))))}
    R_OE OE_TARGET OE 1
    C_OE OE 0 {(RiseDelay+FallDelay)/2+1p}
    B_OF_TARGET OF_TARGET 0 V={((V(LT)<0.8)?0:((V(BIRBO)<0.8)?5:(((V(RBI)<0.8)&&(V(N)<0.5))?5:(((V(N)<0.5)||((V(N)>3.5)&&(V(N)<6.5))||((V(N)>7.5)&&(V(N)<9.5)))?0:5))))}
    R_OF OF_TARGET OF 1
    C_OF OF 0 {(RiseDelay+FallDelay)/2+1p}
    B_OG_TARGET OG_TARGET 0 V={((V(LT)<0.8)?0:((V(BIRBO)<0.8)?5:(((V(RBI)<0.8)&&(V(N)<0.5))?5:((((V(N)>1.5)&&(V(N)<6.5))||((V(N)>7.5)&&(V(N)<9.5)))?0:5))))}
    R_OG OG_TARGET OG 1
    C_OG OG 0 {(RiseDelay+FallDelay)/2+1p}
.ends Param74LS47_8e4368a5
.model Resistor_1d9c8cf9a__R_R1 r(tc1=0 tc2=0 tnom=27)
.model Resistor_1d9c8cf9a__R_R2 r(tc1=0 tc2=0 tnom=27)
.model LM555IIT_c4ad0dd4_ADC adc_bridge(in_low=2.4 in_high=2.6)
.model LM555IIT_c4ad0dd4_DAC dac_bridge(out_low=0 out_high=1 out_undef=0.5)
.model LM555IIT_c4ad0dd4_HIGH d_pullup
.model LM555IIT_c4ad0dd4_LOW d_pulldown
.model LM555IIT_c4ad0dd4_SR d_srlatch(sr_delay=1n enable_delay=1n set_delay=1n reset_delay=1n ic=0 rise_delay=1n fall_delay=1n)
.model LM555IIT_c4ad0dd4_DISCHARGE SW(Ron=10 Roff=1G Vt=0.5 Vh=0.05)
.subckt LM555IIT_c4ad0dd4 T0 T1 T2 T3 T4 T5 T6 T7
    R_CONTROL_TOP T7 T4 10k
    R_CONTROL_BOTTOM T4 T0 20k
    B_SET set_analog T0 V={(V(T3,T0)>0.7 && V(T1,T0)<V(T4,T0)/2) ? 5 : 0}
    B_RESET reset_analog T0 V={(V(T3,T0)<0.7 || V(T5,T0)>V(T4,T0)) ? 5 : 0}
    A_SET [set_analog] [d_set] LM555IIT_c4ad0dd4_ADC
    A_RESET [reset_analog] [d_reset] LM555IIT_c4ad0dd4_ADC
    A_HIGH d_high LM555IIT_c4ad0dd4_HIGH
    A_LOW d_low LM555IIT_c4ad0dd4_LOW
    A_LATCH d_set d_reset d_high d_low d_low d_q d_nq LM555IIT_c4ad0dd4_SR
    A_Q [d_q] [q_analog] LM555IIT_c4ad0dd4_DAC
    A_NQ [d_nq] [nq_analog] LM555IIT_c4ad0dd4_DAC
    B_OUTPUT T2 T0 V={V(T7,T0)*V(q_analog)}
    S_DISCHARGE T6 T0 nq_analog T0 LM555IIT_c4ad0dd4_DISCHARGE
.ends LM555IIT_c4ad0dd4
.subckt Param7SEGMENTCA_ef9d78c1 K1 K2 K3 K4 K5 K6 K7 A params: IS=1e-14 N=1 RS=0 IBV=100P BV=1e30 CJO=0 M=0.5 VJ=1 ION=20m
    .model Param7SEGMENTCA_ef9d78c1_LedDiodeModel D( {IS} {N} {RS} {IBV} {BV} {CJO} {M} {VJ} )

    dd1 A 0vNode1 Param7SEGMENTCA_ef9d78c1_LedDiodeModel
    Vsense1 0vNode1 K1 DC 0
    * Interactive sense node
    b1 lit1 0 v = {((i(Vsense1) < 0) ? 0 : ((i(Vsense1) > ION) ? 1 : i(Vsense1) / ION))}

    dd2 A 0vNode2 Param7SEGMENTCA_ef9d78c1_LedDiodeModel
    Vsense2 0vNode2 K2 DC 0
    * Interactive sense node
    b2 lit2 0 v = {((i(Vsense2) < 0) ? 0 : ((i(Vsense2) > ION) ? 1 : i(Vsense2) / ION))}

    dd3 A 0vNode3 Param7SEGMENTCA_ef9d78c1_LedDiodeModel
    Vsense3 0vNode3 K3 DC 0
    * Interactive sense node
    b3 lit3 0 v = {((i(Vsense3) < 0) ? 0 : ((i(Vsense3) > ION) ? 1 : i(Vsense3) / ION))}

    dd4 A 0vNode4 Param7SEGMENTCA_ef9d78c1_LedDiodeModel
    Vsense4 0vNode4 K4 DC 0
    * Interactive sense node
    b4 lit4 0 v = {((i(Vsense4) < 0) ? 0 : ((i(Vsense4) > ION) ? 1 : i(Vsense4) / ION))}

    dd5 A 0vNode5 Param7SEGMENTCA_ef9d78c1_LedDiodeModel
    Vsense5 0vNode5 K5 DC 0
    * Interactive sense node
    b5 lit5 0 v = {((i(Vsense5) < 0) ? 0 : ((i(Vsense5) > ION) ? 1 : i(Vsense5) / ION))}

    dd6 A 0vNode6 Param7SEGMENTCA_ef9d78c1_LedDiodeModel
    Vsense6 0vNode6 K6 DC 0
    * Interactive sense node
    b6 lit6 0 v = {((i(Vsense6) < 0) ? 0 : ((i(Vsense6) > ION) ? 1 : i(Vsense6) / ION))}

    dd7 A 0vNode7 Param7SEGMENTCA_ef9d78c1_LedDiodeModel
    Vsense7 0vNode7 K7 DC 0
    * Interactive sense node
    b7 lit7 0 v = {((i(Vsense7) < 0) ? 0 : ((i(Vsense7) > ION) ? 1 : i(Vsense7) / ION))}

.ends
.subckt Param74LS193_bebceed8 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
    .model Param74LS193_bebceed8_A2D adc_bridge(in_low=2.5 in_high=2.5)
    .model Param74LS193_bebceed8_D2A dac_bridge(out_low=0 out_high=5 out_undef=2.5)
    AT0_A2D [T0] [d_t0] Param74LS193_bebceed8_A2D
    AT1_A2D [T1] [d_t1] Param74LS193_bebceed8_A2D
    AT2_A2D [T2] [d_t2] Param74LS193_bebceed8_A2D
    AT3_A2D [T3] [d_t3] Param74LS193_bebceed8_A2D
    AT4_A2D [T4] [d_t4] Param74LS193_bebceed8_A2D
    AT5_A2D [T5] [d_t5] Param74LS193_bebceed8_A2D
    AT6_A2D [T6] [d_t6] Param74LS193_bebceed8_A2D
    AT7_A2D [T7] [d_t7] Param74LS193_bebceed8_A2D
    AT8_D2A [d_t8] [T8] Param74LS193_bebceed8_D2A
    AT9_D2A [d_t9] [T9] Param74LS193_bebceed8_D2A
    AT10_D2A [d_t10] [T10] Param74LS193_bebceed8_D2A
    AT11_D2A [d_t11] [T11] Param74LS193_bebceed8_D2A
    AT12_D2A [d_t12] [T12] Param74LS193_bebceed8_D2A
    AT13_D2A [d_t13] [T13] Param74LS193_bebceed8_D2A
    XADAPTER d_t0 d_t1 d_t2 d_t3 d_t4 d_t5 d_t6 d_t7 d_t8 d_t9 d_t10 d_t11 d_t12 d_t13 Param74LS193_bebceed8_SOURCE
.ends Param74LS193_bebceed8
.model Param74LS193_bebceed8_Jkff d_jkff (clk_delay=1e-9 set_delay=1e-9 reset_delay=1e-9 ic=0 rise_delay=1e-9 fall_delay=1e-9)
.model Param74LS193_bebceed8_Inv d_inverter
.model Param74LS193_bebceed8_High d_pullup
.model Param74LS193_bebceed8_NboNand d_nand
.model Param74LS193_bebceed8_NcoNand d_nand
.model Param74LS193_bebceed8_Nand d_nand
.model Param74LS193_bebceed8_And d_and
.model Param74LS193_bebceed8_Nor d_nor
.model Param74LS193_bebceed8_UpCoBuff d_buffer (rise_delay=26ns fall_delay=24ns)
.model Param74LS193_bebceed8_DownBoBuff d_buffer (rise_delay=24ns fall_delay=24ns)
.model Param74LS193_bebceed8_UpQBuff d_buffer (rise_delay=38ns fall_delay=47ns)
.model Param74LS193_bebceed8_DownQBuff d_buffer (rise_delay=38ns fall_delay=47ns)
.model Param74LS193_bebceed8_ClrQBuff d_buffer (fall_delay=35ns)
**********************
*74LS193 SYNCHRONOUS 4-BIT UP/DOWN COUNTER (DUAL CLOCK WITH CLEAR)
***
.subckt Param74LS193_bebceed8_SOURCE A B C D UP DOWN NLOAD CLR QA QB QC QD NBO NCO

    ainv1 DOWN qinv1 Param74LS193_bebceed8_Inv
    ainv2 UP qinv2 Param74LS193_bebceed8_Inv
    ainv3 CLR qinv3 Param74LS193_bebceed8_Inv
    ainv4 NLOAD qinv4 Param74LS193_bebceed8_Inv
    ainv5 qnand1 s1 Param74LS193_bebceed8_Inv
    ainv6 qnand3 s2 Param74LS193_bebceed8_Inv
    ainv7 qnand5 s3 Param74LS193_bebceed8_Inv
    ainv8 qnand7 s4 Param74LS193_bebceed8_Inv


    abuff1 qinv2 buff1 Param74LS193_bebceed8_UpCoBuff
    abuff2 qinv1 buff2 Param74LS193_bebceed8_DownBoBuff
    abuff4 qinv2 buff4 Param74LS193_bebceed8_UpQBuff
    abuff5 qinv1 buff5 Param74LS193_bebceed8_DownQBuff
    abuff6 qinv3 buff6 Param74LS193_bebceed8_ClrQBuff

    anand1 [A qinv4 qinv3] qnand1 Param74LS193_bebceed8_Nand
    anand2 [buff2 nqa nqb nqc nqd] NBO Param74LS193_bebceed8_NboNand
    anand3 [QA QB QC QD buff1] NCO Param74LS193_bebceed8_NcoNand
    anand4 [qnand1 qinv4] qnand2 Param74LS193_bebceed8_Nand
    anand5 [buff6 qnand2] r1 Param74LS193_bebceed8_Nand
    anand6 [B qinv4 qinv3] qnand3 Param74LS193_bebceed8_Nand
    anand7 [qnand3 qinv4] qnand4 Param74LS193_bebceed8_Nand
    anand8 [buff6 qnand4] r2 Param74LS193_bebceed8_Nand
    anand9 [C qinv4 qinv3] qnand5 Param74LS193_bebceed8_Nand
    anand10 [qnand5 qinv4] qnand6 Param74LS193_bebceed8_Nand
    anand11 [buff6 qnand6] r3 Param74LS193_bebceed8_Nand
    anand12 [D qinv4 qinv3] qnand7 Param74LS193_bebceed8_Nand
    anand13 [qnand7 qinv4] qnand8 Param74LS193_bebceed8_Nand
    anand14 [buff6 qnand8] r4 Param74LS193_bebceed8_Nand

    aand1 [buff5 nqa] qand1 Param74LS193_bebceed8_And
    aand2 [QA buff4] qand2 Param74LS193_bebceed8_And
    aand3 [buff5 nqa nqb] qand3 Param74LS193_bebceed8_And
    aand4 [QA QB buff4] qand4 Param74LS193_bebceed8_And
    aand5 [buff5 nqa nqb nqc] qand5 Param74LS193_bebceed8_And
    aand6 [QA QB QC buff4] qand6 Param74LS193_bebceed8_And

    anor1 [buff5 buff4] t1 Param74LS193_bebceed8_Nor
    anor2 [qand1 qand2] t2 Param74LS193_bebceed8_Nor
    anor3 [qand3 qand4] t3 Param74LS193_bebceed8_Nor
    anor4 [qand5 qand6] t4 Param74LS193_bebceed8_Nor

    ah hi Param74LS193_bebceed8_High

    ajkff1 hi hi t1 s1 r1 QA nqa Param74LS193_bebceed8_Jkff
    ajkff2 hi hi t2 s2 r2 QB nqb Param74LS193_bebceed8_Jkff
    ajkff3 hi hi t3 s3 r3 QC nqc Param74LS193_bebceed8_Jkff
    ajkff4 hi hi t4 s4 r4 QD nqd Param74LS193_bebceed8_Jkff
.ENDS Param74LS193_bebceed8_SOURCE

**************************************************
* Simulation settings
**************************************************
.tran 20u 100m 0 20u
.save @R_LAMP1[i] V(XU2.lit1) V(XU2.lit2) V(XU2.lit3) V(XU2.lit4) V(XU2.lit5) V(XU2.lit6) V(XU2.lit7)
.end

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