Logic Circuit

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
V_V1 N1 0 dc 5 ac 0 0 distof1 0 0 distof2 0 0
X_X1 N1 0 N3 0 N1 NAND2x4
E_VP1 VP1 0 N3 0 1

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* Models and supporting definitions follow
**************************************************
.subckt NAND2x4 A B OUT GND VCC VHIGH=5 VTH=2.5

    X1 A B OUT GND VCC NAND2 VTH={VTH}

.ends NAND2x4

* NAND 2-Input gate, ideal behavioral
.subckt NAND2 A1 B1 OUT1 GND1 VCC1 VTH=2.5
    BOUT OUT1 GND1 V = {(V(A1) > VTH) && (V(B1) > VTH) ? GND1 : V(VCC1)}
.ends NAND2

**************************************************
* Simulation settings
**************************************************
.tran 20u 100m 0 20u
.save V(VP1)
.end