Logic Circuit

Components used

SPICE netlist

* **************************************************
* Generated from CircuitSim Schematic
**************************************************
X_U1 N2 0 N3 N2 N2 N4 0 NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 N2 NAND2x4
V_V1 N2 0 dc 5 ac 0 0 distof1 0 0 distof2 0 0
E_VP1 VP1 0 N3 0 1
E_VP2 VP2 0 N4 0 1

**************************************************
* Models and supporting definitions follow
**************************************************
*==============================================================
* 7400 Quad 2-input NAND IC
* Floating inputs are pulled weakly to GND, treated as logic 0
*   NAND output defaults to VHIGH (logic 1)
*==============================================================
.subckt NAND2x4 a1 b1 y1 a2 b2 y2 gnd y3 a3 b3 y4 a4 b4 vcc
    + VHIGH=5 VTH=2.5 Rpull=1Meg

    * Weak pull-downs (make floating pins = 0 V)
    * Prevents Spice hanging if not all pins connected
    R1A a1 gnd {Rpull}
    R1B b1 gnd {Rpull}
    R2A a2 gnd {Rpull}
    R2B b2 gnd {Rpull}
    R3A a3 gnd {Rpull}
    R3B b3 gnd {Rpull}
    R4A a4 gnd {Rpull}
    R4B b4 gnd {Rpull}

    X1 a1 b1 y1 gnd NAND2 VHIGH={VHIGH} VTH={VTH}
    X2 a2 b2 y2 gnd NAND2 VHIGH={VHIGH} VTH={VTH}
    X3 a3 b3 y3 gnd NAND2 VHIGH={VHIGH} VTH={VTH}
    X4 a4 b4 y4 gnd NAND2 VHIGH={VHIGH} VTH={VTH}

.ends NAND2x4

* NAND 2-Input gate, ideal behavioral
*  (Copied from NAND gate by CircuitSim)
.subckt NAND2 A B OUT GND VHIGH=5 VTH=2.5
    BOUT OUT GND V = {(V(A) > VTH) && (V(B) > VTH) ? 0 : VHIGH}
.ends NAND2

**************************************************
* Simulation settings
**************************************************
.tran 20u 100m 0 20u
.save V(VP1) V(VP2)
.end