4-Bit PIPO Register
Digital
·
Generic
·
Curated by CircuitSim
Details
Manufacturer
Generic
Part number
—
Pins
11
Used in
No circuits
Added
Sep 2026
About this component
Four-bit rising-edge parallel-in/parallel-out register. Active-high LOAD captures D0–D3; low LOAD holds state, and active-high CLEAR asynchronously resets all outputs.
Parameters
Logic levels
2 parameters
VTH
Input threshold
Voltage at or above which an input is interpreted as logic high.
2.5 V
VHIGH
High output voltage
Voltage driven for a defined logic-high output.
5 V
Timing and state
2 parameters
TPD
Propagation delay
Clock, clear, and output transition delay used by the ideal edge-triggered stages.
1n s
INITIAL_STATE
Initial state
Initial unsigned four-bit state from 0 to 15; bit n initializes Qn.
0
Pins
Pins
11 pins
1
D0
Parallel data bit 0 and least-significant state bit.
2
D1
Parallel data bit 1.
3
D2
Parallel data bit 2.
4
D3
Parallel data bit 3 and most-significant state bit.
5
LOAD
Active-high synchronous parallel-load control.
6
CLK
Rising-edge clock input.
7
CLEAR
Active-high asynchronous clear; highest-priority control.
8
Q0
Registered output bit 0.
9
Q1
Registered output bit 1.
10
Q2
Registered output bit 2.
11
Q3
Registered output bit 3.
Public circuits using this component
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