4-Bit SIPO Shift Register
Digital
·
Generic
·
Curated by CircuitSim
Details
Manufacturer
Generic
Part number
—
Pins
8
Used in
No circuits
Added
Sep 2026
About this component
Four-bit rising-edge serial-in/parallel-out shift register. SER_IN enters Q0 and shifts toward Q3 while ENABLE is high; all four state bits remain directly observable.
Parameters
Logic levels
2 parameters
VTH
Input threshold
Voltage at or above which an input is interpreted as logic high.
2.5 V
VHIGH
High output voltage
Voltage driven for a defined logic-high output.
5 V
Timing and state
2 parameters
TPD
Propagation delay
Clock, clear, and output transition delay used by the ideal edge-triggered stages.
1n s
INITIAL_STATE
Initial state
Initial unsigned four-bit state from 0 to 15; bit n initializes Qn.
0
Pins
Pins
8 pins
1
SER_IN
Serial input entering state bit Q0.
2
ENABLE
Active-high synchronous shift enable.
3
CLK
Rising-edge clock input.
4
CLEAR
Active-high asynchronous clear; highest-priority control.
5
Q0
Parallel output bit 0; newest shifted bit.
6
Q1
Parallel output bit 1.
7
Q2
Parallel output bit 2.
8
Q3
Parallel output bit 3; oldest retained shifted bit.
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