4-Bit PISO Shift Register
Digital
·
Generic
·
Curated by CircuitSim
Details
Manufacturer
Generic
Part number
—
Pins
10
Used in
No circuits
Added
Sep 2026
About this component
Four-bit rising-edge parallel-in/serial-out shift register. LOAD captures D0–D3 with priority over ENABLE; enabled shifts move Q0 toward Q3/SER_OUT while SER_IN enters Q0.
Parameters
Logic levels
2 parameters
VTH
Input threshold
Voltage at or above which an input is interpreted as logic high.
2.5 V
VHIGH
High output voltage
Voltage driven for a defined logic-high output.
5 V
Timing and state
2 parameters
TPD
Propagation delay
Clock, clear, and output transition delay used by the ideal edge-triggered stages.
1n s
INITIAL_STATE
Initial state
Initial unsigned four-bit state from 0 to 15; bit n initializes Qn.
0
Pins
Pins
10 pins
1
D0
Parallel-load bit 0 and least-significant state bit.
2
D1
Parallel-load bit 1.
3
D2
Parallel-load bit 2.
4
D3
Parallel-load bit 3 and first serial-output bit after load.
5
SER_IN
Serial input entering Q0 during enabled shifts.
6
LOAD
Active-high synchronous parallel-load control; priority over ENABLE.
7
ENABLE
Active-high synchronous shift enable when LOAD is low.
8
CLK
Rising-edge clock input.
9
CLEAR
Active-high asynchronous clear; highest-priority control.
10
SER_OUT
Serial output from state bit Q3.
Public circuits using this component
No public circuits are using this component yet.
Drop 4-Bit PISO Shift Register into your circuit
Official component · simulated with full SPICE accuracy · free to get started.