RAM 4×4
Digital
·
Generic
·
Curated by CircuitSim
Details
Manufacturer
Generic
Part number
—
Pins
13
Used in
No circuits
Added
Sep 2026
About this component
Four-word by four-bit RAM for register-transfer lessons. WE writes D0–D3 to address A1:A0 on the rising CLK edge; readback is asynchronous through active-high OE, and each initial word is editable.
Parameters
Logic levels
2 parameters
VTH
Input threshold
Voltage at or above which an input is interpreted as logic high.
2.5 V
VHIGH
High output voltage
Voltage driven for a logic-high output.
5 V
Timing
1 parameter
TPD
Propagation delay
Clock-to-state transition delay for each ideal storage bit.
1n s
Initial contents
4 parameters
IW0
Initial word 0
Deterministic unsigned four-bit power-up value for address 0; bit 0 maps to Q0.
0
IW1
Initial word 1
Deterministic unsigned four-bit power-up value for address 1; bit 0 maps to Q0.
0
IW2
Initial word 2
Deterministic unsigned four-bit power-up value for address 2; bit 0 maps to Q0.
0
IW3
Initial word 3
Deterministic unsigned four-bit power-up value for address 3; bit 0 maps to Q0.
0
Pins
Pins
13 pins
1
A0
Address bit 0 and least-significant address bit.
2
A1
Address bit 1.
3
D0
Write-data bit 0 and least-significant data bit.
4
D1
Write-data bit 1.
5
D2
Write-data bit 2.
6
D3
Write-data bit 3 and most-significant data bit.
7
WE
Active-high write enable sampled on the rising clock edge.
8
CLK
Rising-edge write clock.
9
OE
Active-high asynchronous output enable; low forces outputs low.
10
Q0
Read-data bit 0 and least-significant data bit.
11
Q1
Read-data bit 1.
12
Q2
Read-data bit 2.
13
Q3
Read-data bit 3 and most-significant data bit.
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